Abstract: Charge on a floating gate of a semiconductor device structure is neutralized by illuminating the structure with a high intensity light during process steps that inject charge. The light provides for the formation of electrons, or free carriers, in the semiconductor substrate. The electrons facilitate tunneling which prevents dielectric degradation or rupture.

Abstract: A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers.

Abstract: An active portion of a cell of a static RAM semiconductor device comprising a MOSFET and a variable resistor load device having non-diffused contacts which are self-aligned is described. A polycrystalline gate is used as a mask for the implantation of a source and a drain into a semiconductor substrate. Following the formation of a conformal dielectric layer and a conformal polycrystalline layer PtSi contacts are formed. These contacts are also aligned by the gate and do not diffuse and therefore may be spaced closely together. As the MOSFET of the device is turned "on" and "off" the resistance of the load device increases and decreases proportionately.

Abstract: A method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" (dummy) gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material (refractory metal) is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alternatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub.

Abstract: Radiation hard, N-channel MOS devices comprising active regions surrounded by field oxide protected by an underlying region of heavily doped p-type material. The guard region is doped heavily enough to provide field inversion voltages in the range of 50 V to 60 V prior to irradiation. The guard region is separated from the source and drain regions to provide acceptably high breakdown voltages. The devices are produced with minor variations to well known, high density local oxidation of silicon-type processes.

Abstract: In a channel formed in one surface of a semiconductor substrate having a first conductivity, e.g. N type, a layer of material having a second conductivity type, e.g. P type boron, and a layer of relatively low resistance material such as Tungsten in contact with the first layer but insulated from the substrate. Second conductivity type tubs and the like can be formed adjacent the bus and in direct contact therewith through the first layer.

Abstract: A self-aligned MOS transistor having improved operating characteristics and higher packing density and a method for fabricating the device. Resistance of the gate electrode is reduced substantially by forming the electrode of a metal silicide. Resistance of the source and drain regions is likewise reduced substantially by forming a metal silicide in the doped junction region which allows those regions to be smaller and to require less area. The silicided source and drain regions are self-aligned with and closely spaced to the silicided gate electrode. This is provided by a process which utilizes and makes possible an undercut etching of a polycrystalline silicon gate electrode.

Abstract: A method for manufacturing high speed semiconductor devices by selectively reducing the minority carrier lifetime in regions susceptible to minority carrier charge storage. The selective reduction is achieved by implanting ions of low atomic weight into the surface of the semiconductor crystal in order to locally reduce the sub-surface lifetime.