Abstract: An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.

Abstract: A system and method of mapping of a processing task to a target processor is provided. Kernels associated with unit of processing defined for a processor to operate on a processing operation on the target processor required to performing the processing task. A directed acyclic graph (DAG) comprising the kernels and specifying connections between the one or more kernels represents the desired processing task to be executed by the target processor is resolved from the kernels defined in the DAG to a process executed by a processor architecture of the target processor. Data sequencing is determined from the DAG for memory usage in executing the process. Host code is generated to configure and execute the process in relation to the kernel execution for the process resolved for the processing task.

Abstract: A system and method of mapping of a processing task to a target processor is provided. Kernels associated with unit of processing defined for a processor to operate on a processing operation on the target processor required to performing the processing task. A directed acyclic graph (DAG) comprising the kernels and specifying connections between the one or more kernels represents the desired processing task to be executed by the target processor is resolved from the kernels defined in the DAG to a process executed by a processor architecture of the target processor. Data sequencing is determined from the DAG for memory usage in executing the process. Host code is generated to configure and execute the process in relation to the kernel execution for the process resolved for the processing task.

Abstract: An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.

Abstract: An electronic camera for capturing and storing images includes an image capture section and an image processing section. The image capture section includes an image sensor for capturing an image and producing pixel data representative of the captured image, an analog-to-digital (A/D) converter for digitizing the pixel data, and a horizontal shift register responsive to applied vertical clock signals for receiving lines of the pixel data from the image sensor and responsive to applied horizontal clock signals for sequentially transferring the lines of pixel data to the A/D converter, the time between the application of horizontal and vertical clock signals providing for a vertical transfer interval wherein pixel data is prevented from being output from the horizontal shift register.

Abstract: Adaptive interpolation is performed by apparatus operating upon a digitized image signal obtained from an image sensor having color photosites that generate a plurality of color values, but only one color per photosite. A digital processor obtains gradient values from the differences between chrominance values in vertical and horizontal image directions. The gradient values are compared with each other in order to select one of the directions as the preferred orientation for the interpolation of additional luminance values. The interpolation is then performed upon values selected to agree with the preferred orientation.