Abstract: The invention relates to a server (100) comprising a plurality of information processing modules (1, 2, 3) so as to form a unified platform for an operating system deployed on the server, each module having an elementary software, BIOS (13, 23), provided to use configuration data when the module is started up, the server also being provided to allow at least one configuration datum to be modified, and being characterized in that it further comprises a management controller, BMC (12, 22), provided to store configuration data in an associated memory (14, 24), and to transmit, when the at least one configuration datum is modified, such data to management controllers associated with the other modules, and in that the elementary software is provided to recover the configuration data from the management controller when the module is started up.

Abstract: A method of obtaining information stored in registers of at least one processing module of a computer, each processing module including a management controller to read the information stored in the associated registers, and a programmable logic circuit to trigger a requested reset following a fatal error, the method including in the event of reception of a reset request by a programmable logic circuit of a processing module, suspending by the programmable logic circuit the triggering of the reset and alerting the associated management controller of the occurrence of a fatal error, and, if the associated management controller is capable thereof, reading by the associated management controller the information stored in associated and chosen registers then storing by the associated management controller the read information in a file, and authorizing said associated programmable logic circuit to trigger said requested reset.

Abstract: A method is provided for facilitating access by an external user to the internal registers of a server including: transmitting access commands originating from the external user to a service processor using a communication protocol directly understandable by the service processor which accesses the internal registers using one or more access protocols, automatically transforming command lines issued by the user into access commands in the communication protocol using one or more service modules which associate at least the corresponding addresses of the internal registers with the names of the internal registers supplied by the external user. On the occasion of a user-commanded access by the service processor to the internal registers, the service processor is responsible for managing a possible risk of collision with a monitoring access to the internal registers for the purposes of updating a copy of the status of the internal registers.

Abstract: A server (100) having a plurality of modules (1-8), each module including a communication element (16, 26), a plurality of processors (CPU) (10, 11, 20, 21), a system on a chip (SOC) (12, 22) executing firmware, and a network of programmable ports (FPGA) (13, 23). The modules interconnected by an interconnection (27) between each communication element, an interconnection (28) between each system on a chip (SOC). The executed firmware produces two software components: a satellite management controller (SMC) component of the system (15, 25) and a baseboard management controller (BMC) component (14, 24).

Abstract: A method of obtaining information stored in registers of at least one processing module of a computer, each processing module including a management controller to read the information stored in the associated registers, and a programmable logic circuit to trigger a requested reset following a fatal error, the method including in the event of reception of a reset request by a programmable logic circuit of a processing module, suspending by the programmable logic circuit the triggering of the reset and alerting the associated management controller of the occurrence of a fatal error, and, if the associated management controller is capable thereof, reading by the associated management controller the information stored in associated and chosen registers then storing by the associated management controller the read information in a file, and authorizing said associated programmable logic circuit to trigger said requested reset.

Abstract: A server (100) having a plurality of modules (1-8), each module including a communication element (16, 26), a plurality of processors (CPU) (10, 11, 20, 21), a system on a chip (SOC) (12, 22) executing firmware, and a network of programmable ports (FPGA) (13, 23). The modules interconnected by an interconnection (27) between each communication element, an interconnection (28) between each system on a chip (SOC). The executed firmware produces two software components: a satellite management controller (SMC) component of the system (15, 25) and a baseboard management controller (BMC) component (14, 24).

Abstract: A method is provided for facilitating access by an external user to the internal registers of a server including: transmitting access commands originating from the external user to a service processor using a communication protocol directly understandable by the service processor which accesses the internal registers using one or more access protocols, automatically transforming command lines issued by the user into access commands in the communication protocol using one or more service modules which associate at least the corresponding addresses of the internal registers with the names of the internal registers supplied by the external user. On the occasion of a user-commanded access by the service processor to the internal registers, the service processor is responsible for managing a possible risk of collision with a monitoring access to the internal registers for the purposes of updating a copy of the status of the internal registers.

Abstract: A test monitor for a multiprocessor machine including a plurality of processors each configured to execute a test by interpreting a script language for writing tests, in which one of the processors executes a kernel part comprising instructions for conducting and monitoring the executed tests according to the scripts, and an application program interface provided using a library of functions for interfacing with firmware of the multiprocessor machine. The test monitor includes a method for executing instruction sequences simultaneously in several processors of a multiprocessor machine.

Abstract: A test monitor loaded into a multiprocessor machine comprises a program (31) designed to interpret a script language for writing tests, a program (29) that constitutes a kernel part for conducting the tests according to the scripts, and a library (30) of functions that constitutes an application program interface with the firmware of the machine 1. This monitor implements a method for executing instruction sequences simultaneously in several processors (3, 4, 5) of a multiprocessor machine (1). The method comprises a first step (8) in which a single processor operating system is booted in a first processor (2) and a second step (9) in which the first processor (1) orders at least one other processor (3) of the machine, called an application processor, to execute one or more instruction sequences (17, 18, 19) under the control of said first processor.

Abstract: A test monitor loaded into a multiprocessor machine comprises a program (31) designed to interpret a script language for writing tests, a program (29) that constitutes a kernel part for conducting the tests according to the scripts, and a library (30) of functions that constitutes an application program interface with the firmware of the machine 1. This monitor implements a method for executing instruction sequences simultaneously in several processors (3, 4, 5) of a multiprocessor machine (1). The method comprises a first step (8) in which a single processor operating system is booted in a first processor (2) and a second step (9) in which the first processor (1) orders at least one other processor (3) of the machine, called an application processor, to execute one or more instruction sequences (17, 18, 19) under the control of said first processor.

Abstract: A test monitor loaded into a multiprocessor machine comprises a program (31) designed to interpret a script language for writing tests, a program (29) that constitutes a kernel part for conducting the tests according to the scripts, and a library (30) of functions that constitutes an application program interface with the firmware of the machine 1. This monitor implements a method for executing instruction sequences simultaneously in several processors (3, 4, 5) of a multiprocessor machine (1). The method comprises a first step (8) in which a single processor operating system is booted in a first processor (2) and a second step (9) in which the first processor (1) orders at least one other processor (3) of the machine, called an application processor, to execute one or more instruction sequences (17, 18, 19) under the control of said first processor.