Abstract: Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

Abstract: Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programming methods that use specific biasing of array lines to provide sufficient programming currents through only selected cells.

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

Abstract: Under one aspect, a nanotube diode includes: a cathode formed of a semiconductor material; and an anode formed of nanotubes. The cathode and anode are in fixed and direct physical contact, and are constructed and arranged such that sufficient electrical stimulus applied to the cathode and the anode creates a conductive pathway between the cathode and the anode. In some embodiments, the anode includes a non-woven nanotube fabric having a plurality of unaligned nanotubes. The non-woven nanotube fabric may have a thickness, e.g., of 0.5 to 20 nm. Or, the non-woven nanotube fabric may include a block of nanotubes. The nanotubes may include metallic nanotubes and semiconducting nanotubes, and the cathode may include an n-type semiconductor material. A Schottky barrier can form between the n-type semiconductor material and the metallic nanotubes and/or a PN junction can form between the n-type semiconductor material and the semiconducting nanotubes.

Abstract: Device structures and methods for providing carbon nanotube field effect transistor (CNTFET) devices with enhanced current carrying capability at lower densities are disclosed. Apparatuses and methods using CNTFET devices for providing protection from electrostatic discharge (ESD) voltages are also disclosed. According to some aspects of the present disclosure the electrostatic discharge protection circuits are configured with CNTFET diodes and provide protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit. According to some aspects of the present disclosure the methods for providing protection from electrostatic discharge voltages create conducting paths for providing protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit.

Abstract: Device structures and methods for providing carbon nanotube field effect transistor (CNTFET) devices with enhanced current carrying capability at lower densities are disclosed. Apparatuses and methods using CNTFET devices for providing protection from electrostatic discharge (ESD) voltages are also disclosed. According to some aspects of the present disclosure the electrostatic discharge protection circuits are configured with CNTFET diodes and provide protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit. According to some aspects of the present disclosure the methods for providing protection from electrostatic discharge voltages create conducting paths for providing protection from electrostatic discharge induced voltages for a protected circuit without affecting the normal operation of the protected circuit.

Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: Field effect devices having a drain controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconductor type. The source region is connected to a corresponding terminal. A gate structure is disposed over the channel region and connected to a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.

Abstract: Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits.

Abstract: An electrostatic discharge (ESD) protection circuit for protecting a protected circuit is coupled to an input pad. The ESD circuit includes a nanotube switch electrically having a control. The switch is coupled to the protected circuit and to a discharge path. The nanotube switch is controllable, in response to electrical stimulation of the control, between a de-activated state and an activated state. The activated state creates a current path so that a signal on the input pad flows to the discharge path to cause the signal at the input pad to remain within a predefined operable range for the protected circuit. The nanotube switch, the input pad, and the protected circuit may be on a semiconductor chip. The nanotube switch may be on a chip carrier. The deactivated and activated states may be volatile or non-volatile depending on the embodiment.

Abstract: Under one aspect, a method of cooling a circuit element includes providing a thermal reservoir having a temperature lower than an operating temperature of the circuit element; and providing a nanotube article in thermal contact with the circuit element and with the reservoir, the nanotube article including a non-woven fabric of nanotubes in contact with other nanotubes to define a plurality of thermal pathways along the article, the nanotube article having a nanotube density and a shape selected such that the nanotube article is capable of transferring heat from the circuit element to the thermal reservoir.

Abstract: NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in electrical communication with first and second conductor layers. A memory operation circuit including a circuit for generating and applying a select signal on first and second conductor layers to induce a change in the resistance of the nanotube fabric layer between the first and second conductor layers is provided. At least two adjacent memory cells are formed in at least two selected cross sections of the nanotube fabric and conductor layers such that each memory cell is uniquely addressable and programmable. For each cell, a change in resistance corresponds to a change in an informational state of the memory cell. Some embodiments include bit lines, word lines, and reference lines. In some embodiments, 6F2 memory cell density is achieved.

Abstract: A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.