Abstract: There is disclosed a multiplier structure including elementary multipliers and a matrix of binary adder cells of the high-speed carry propagation type associated with the elementary multipliers. The intermediate results to be added are transferred along a matrix diagonal from each adder cell to an adder cell p lines and p columns distant therefrom, where p is a whole number greater than one. The matrix of binary adder cells does not contain cells associated with the first p lines and columns of elementary multipliers and is supplemented by p-1 columns or lines of additional cells on the output side of the matrix furnishing the least significant bits and by p lines or columns of additional cells on the output side of the matrix furnishing the most significant bits. The additional adder cells serve to gather the intermediate results furnished by the adder cells of the p adjacent columns and lines of the associated matrix in order to produce the bits of the final product.

Abstract: This ringing circuit detects the presence of the ringing signal on the subscriber line by means of a first circuit for detecting transition of the same direction in the ringing signal and of a second time measuring circuit for defining a validity window for the occurrence of a transition of desired direction and for providing a ringing control signal when the ringing signal is recognized. The ringing circuit is supplied by rectified AC ringing signals wherein a sufficient-voltage detection circuit is provided to authorized the operation of the ringing circuit.

Abstract: A counter comprising MOS transistor cells providing a tree like network. The logic value 1 is shifted to the left (bits of highest weight or rank) as many times as there are input binary variables with the logic value 1. The corresponding output is then at level 1 and all the other outputs are at logic level 0. An adder is obtained by providing a NOR gate decoding arrangement connected to the outputs of the counter.