Abstract: A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path including circuits for checking and correcting errors when an error condition has been detected. An auxiliary memory is provided for storing error flag bits indicating memory zones which have produced erroneous readouts, whereby the system is controlled such that high speed direct read cycles are executed for no-error memory zones and optimum memory accessing time is achieved without sacrificing the reliability achieved through use of the error correcting codes.

Abstract: A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two "bytes", of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded.