Patents by Inventor Claudio Mucci
Claudio Mucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9219481Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.Type: GrantFiled: February 6, 2015Date of Patent: December 22, 2015Assignee: STMicroelectronics S.r.l.Inventors: Mauro Scandiuzzo, Salvatore Valerio Cani, Claudio Mucci, Roberto Canegallo, Pier Luigi Rolandi
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Publication number: 20150155874Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.Type: ApplicationFiled: February 6, 2015Publication date: June 4, 2015Inventors: Mauro SCANDIUZZO, Salvatore Valerio CANI, Claudio Mucci, Roberto Canegallo, Pier Luigi Rolandi
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Patent number: 8981830Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.Type: GrantFiled: January 29, 2013Date of Patent: March 17, 2015Assignee: STMicroelectronics S.r.l.Inventors: Mauro Scandiuzzo, Salvatore Valerio Cani, Claudio Mucci, Roberto Canegallo, Pier Luigi Rolandi
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Patent number: 8910103Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.Type: GrantFiled: December 28, 2009Date of Patent: December 9, 2014Assignee: STMicroelectronics S.r.l.Inventors: Fabio Campi, Claudio Mucci, Stefano Pucillo, Luca Ciccarelli, Valentina Nardone
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Patent number: 8411492Abstract: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.Type: GrantFiled: April 29, 2011Date of Patent: April 2, 2013Assignee: STMicroelectronics S.R.L.Inventors: Valentina Nardone, Stefano Pucillo, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Luca Perugini
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Patent number: 8390330Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.Type: GrantFiled: April 28, 2011Date of Patent: March 5, 2013Assignee: STMicroelectronics S.R.L.Inventors: Luca Ciccarelli, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Valentina Nardone
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Publication number: 20120075920Abstract: A memory base cell stores a bit of information implemented from a regular and compact structure made up of multiple identical and replicated base elements, on the “sea of gates” Model, in which the base element of the structure is a cell able to be configured with a minimum width in relation to the particular technology used. Such a cell includes a bistable element with an input node operatively connected to a writing data line of the memory base cell, and an output node operatively connected to a reading data line of the memory base cell. The bistable element also has a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node of the bistable element.Type: ApplicationFiled: April 29, 2011Publication date: March 29, 2012Applicant: STMicroelectronics S.r.I.Inventors: Valentina NARDONE, Stefano Pucillo, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Luca Perugini
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Publication number: 20120001655Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.Type: ApplicationFiled: April 28, 2011Publication date: January 5, 2012Applicant: STMicroelectronics S.r.I.Inventors: Luca CICCARELLI, Roberto Canegallo, Claudio Mucci, Massimiliano Innocenti, Valentina Nardone
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Patent number: 7965107Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.Type: GrantFiled: December 28, 2009Date of Patent: June 21, 2011Assignee: STMicroelectronics S.r.l.Inventors: Luca Ciccarelli, Lorenzo Cali, Massimiliano Innocenti, Claudio Mucci, Valentina Nardone, Matteo Pizzotti, Pankaj Rohilla
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Publication number: 20100169857Abstract: A method is for designing an accelerator for digital signal processing including defining a software programmable fully pre-laid out macro by pre-laying out with a fixed topology a control logic of the DSP accelerator to obtain a fully pre-laid out control logic. The method further includes defining a hardware programmable partially pre-laid out macro by customizing a configurable layout area, thereby mapping a computational logic based on computation kernels related to an application of the DSP accelerator. A partially pre-laid out computational logic is therefore obtained.Type: ApplicationFiled: December 28, 2009Publication date: July 1, 2010Applicant: STMicroelectronics S.r.I.Inventors: Fabio Campi, Claudio Mucci, Stefano Pucillo, Luca Ciccarelli, Valentina Nardone
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Publication number: 20100164547Abstract: A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates.Type: ApplicationFiled: December 28, 2009Publication date: July 1, 2010Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS PVT. LTD.Inventors: Luca Ciccarelli, Lorenzo Cali, Massimiliano Innocenti, Claudio Mucci, Valentina Nardone, Matteo Pizzotti, Pankaj Rohilla