Patents by Inventor Claudio Nava
Claudio Nava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804264Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.Type: GrantFiled: September 13, 2022Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventors: Paolo Fantini, Andrea Martinelli, Claudio Nava
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Publication number: 20230071663Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.Type: ApplicationFiled: September 13, 2022Publication date: March 9, 2023Inventors: Paolo Fantini, Andrea Martinelli, Claudio Nava
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Publication number: 20220336015Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Paolo Fantini, Andrea Martinelli, Claudio Nava
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Patent number: 11475947Abstract: Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.Type: GrantFiled: April 15, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Paolo Fantini, Andrea Martinelli, Claudio Nava
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Publication number: 20220100404Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.Type: ApplicationFiled: October 5, 2021Publication date: March 31, 2022Inventors: Andrea Martinelli, Christopher Vincent Antoine Laurent, Claudio Nava, Marco Defendi
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Patent number: 11144228Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.Type: GrantFiled: July 11, 2019Date of Patent: October 12, 2021Assignee: Micron Technology, Inc.Inventors: Andrea Martinelli, Christophe Vincent Antoine Laurent, Claudio Nava, Marco Defendi
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Publication number: 20210011645Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.Type: ApplicationFiled: July 11, 2019Publication date: January 14, 2021Inventors: Andrea Martinelli, Christophe Vincent Antoine Laurent, Claudio Nava, Marco Defendi
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Publication number: 20180170318Abstract: An operating fluid storage system for a motor vehicle having a reservoir with a filling opening and a closure cover which closes the filling opening and which can be removed from said filling opening to release the filling opening, and with at least one operating fluid outlet opening, to which an operating fluid conveyor line can be connected, for the output of operating fluid to a consumer, the system having a need sensor assembly and an output device, the need sensor assembly determines a filling need of the reservoir and outputs a corresponding need signal to the output device which acoustically, visually and/or haptically outputs a signal indicating the filling need; on the reservoir, an identification device is provided, which can be switched between at least two functional states and which is connected to the need sensor assembly via signal transmission, and which, when the need sensor assembly determines a filling need of the reservoir, is actuated by a corresponding need signal of the need sensor asseType: ApplicationFiled: December 12, 2017Publication date: June 21, 2018Inventors: Walter Kral, Christoph Ganthaler, Claudio Nava, Michael Purps
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Patent number: 7965561Abstract: A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address codes of the plurality of memory cells and to generate a plurality of decoding and selecting signals in response to the address codes. A plurality of second decoding circuits are coupled to the first decoding circuit and operable to generate driving signals for the memory cell address signal lines based at least in part on the plurality of decoding and selecting signals. A voltage shifting circuit is operable to generate a shift in the voltage of the plurality of decoding and selecting signals for generating a plurality of shifted voltage decoding and selecting signals and to provide the shifted decoding and selecting signals to the plurality of second decoding signals for generating the drive signals.Type: GrantFiled: February 8, 2007Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventors: Pierguido Garofalo, Efrem Bolandrina, Claudio Nava
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Patent number: 7911290Abstract: A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.Type: GrantFiled: November 16, 2006Date of Patent: March 22, 2011Assignee: STMicroelectronics S.r.l.Inventors: Daniele Vimercati, Claudio Nava, Christophe Laurent
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Patent number: 7596023Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: GrantFiled: November 2, 2007Date of Patent: September 29, 2009Inventors: Alessandro Magnavacca, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Publication number: 20080106937Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: ApplicationFiled: November 2, 2007Publication date: May 8, 2008Applicant: STMicroelectronics S.r.I.Inventors: Alessandro MAGNAVACCA, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Publication number: 20070195605Abstract: A memory device including a plurality of memory cells, said memory cells being grouped in at least two memory sectors. In each memory sector the memory cells are arranged according to a plurality of alignments of memory cells. A respective memory cell access signal line is associated with each alignment. A first decoding circuit is adapted to receive an address code of the memory cells and in response thereto asserts a plurality of decoding and selecting signals common to said at least two memory sectors. A respective second decoding circuit, associated with each one of the at least two memory sectors, is operatively coupled to the first decoding circuit and adapted to generate driving signals for said memory cell access signal lines depending at least in part on said decoding and selecting signals.Type: ApplicationFiled: February 8, 2007Publication date: August 23, 2007Applicant: STMICROELECTRONICS S.R.L.Inventors: Pierguido Garofalo, Efrem Bolandrina, Claudio Nava
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Publication number: 20070133666Abstract: A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.Type: ApplicationFiled: November 16, 2006Publication date: June 14, 2007Applicant: STMicroelectronics S.r.l.Inventors: Daniele Vimercati, Claudio Nava, Christophe Laurent
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Patent number: 6339551Abstract: A semiconductor device includes at least two pads for the input of external signals and/or for the output of signals from said semiconductor device, at least two uncoupling buffers each connected to each one of said pads, at least one multiplexer connected to said pads by means of said uncoupling buffers and at least one memory element suitable to generate a configuration signal operating on said multiplexer and said uncoupling buffers to selectively enable one or the other of said pads.Type: GrantFiled: April 27, 2000Date of Patent: January 15, 2002Assignee: STMicroelectronics S.r.l.Inventors: Simone Bartoli, Mauro Sali, Claudio Nava, Antonio Russo
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Patent number: D523794Type: GrantFiled: November 24, 2004Date of Patent: June 27, 2006Assignee: Freni Brembo S.p.A.Inventors: Fortunato Strumbo, Claudio Nava