Abstract: A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are connected in pairs from two adjacent blocks in each case to a common sense amplifier and the sense amplifiers are disposed between the cell blocks. In which case bit line switches are disposed in sense amplifier strips—lying between the blocks—between in each case two adjacent sense amplifiers in order to momentarily connect the other ends—not connected to the sense amplifiers—of two bit line pairs from the adjacent cell blocks during a precharge phase of a bit line pair activated directly beforehand. The precharge phase takes place at the start of a charge equalization phase.

Abstract: A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic conditions in a real application environment. In practice, such components are normally firmly soldered in on a module carrier. Owing to the thermal load during soldering, this solution cannot always be used and, furthermore, the contacts that are made should be detachable. Commercially available contact bases with detachable contacts cannot be used, however, since their dimensions are too large and they do not fit in the available surface area on the module carrier. The novel contact base is sufficiently small that a plurality of contact bases can be arranged closely one next to the other in a row in a very small space on a module carrier. The module carrier has plug contacts to be plugged into a commercial socket in order to make contact.

Abstract: A dynamic RAM semiconductor memory with a shared sense amplifier organization concept, in which the cell arrays are subdivided into blocks whose bit lines are connected in pairs from two adjacent blocks in each case to a common sense amplifier and the sense amplifiers are disposed between the cell blocks. In which case bit line switches are disposed in sense amplifier strips—lying between the blocks—between in each case two adjacent sense amplifiers in order to momentarily connect the other ends—not connected to the sense amplifiers—of two bit line pairs from the adjacent cell blocks during a precharge phase of a bit line pair activated directly beforehand. The precharge phase takes place at the start of a charge equalization phase.

Abstract: An integrated memory circuit has a memory cell array and a test circuit. The memory cell array is formed with memory areas each having a number of cells. The test circuit generates error information during testing of an addressed memory area. The error information indicates if at least one of the cells of the addressed memory area is faulty. A storage element is provided which, given the occurrence of an error in the addressed memory area, stores information with the aid of which the faulty memory cell of the faulty area can be identified.

Abstract: A frequent problem that arises in particular with regard to the analysis of memory components is that the memory components have to be tested under realistic conditions in a real application environment. In practice, such components are normally firmly soldered in on a module carrier. Owing to the thermal load during soldering, this solution cannot always be used and, furthermore, the contacts that are made should be detachable. Commercially available contact bases with detachable contacts cannot be used, however, since their dimensions are too large and they do not fit in the available surface area on the module carrier. The novel contact base is sufficiently small that a plurality of contact bases can be arranged closely one next to the other in a row in a very small space on a module carrier. The module carrier has plug contacts to be plugged into a commercial socket in order to make contact.