Abstract: A CMOS device includes a p-type substrate and an isolated PWell region. An isolation region has an NWell region abutting a perimeter of the PWell region. The isolation region includes a DNWell region positioned below the PWell region and an NWell region. The NWell region forms a sidewall of a tub and the DNWell region forms a bottom of the tub. The tub is an n-type region that physically and electrically isolates an enclosed PWell region from the p-type substrate. A NTN region is formed in the p-type substrate and at least partially abuts an outer perimeter of the NWell region. The NTN region is defined as a non-PWell and a non-NWell region. The NTN region enhances electrical isolation of the circuits inside the PWell region from circuits outside of the PWell region. In one embodiment, the high-frequency performance of an NMOSFET inside the isolated PWell is improved because of the reduced sidewall capacitance with the NTN region.

Abstract: A content addressable memory cell may include a non-volatile memory storage transistor coupled to an enhancement transistor. In some embodiments, the enhancement transistor may be a select cell. In some embodiments, the storage transistor may use substrate hot electron injection. Through the use of the enhancement transistor, overerasing and read disturb problems may be mitigated.

Abstract: A power amplifier utilizes cascode arrangements to achieve target performance levels for a power amplifier, such as the type used in wireless communication devices. A negative resistance circuit is provided for the cascode arrangement such that high gain, or oscillation, is promoted during operation of the power amplifier. In one embodiment, the negative resistance circuit includes cross-coupling transistors. Various features are provided in order to reduce the susceptibility of the power amplifier to voltage breakdown while maintaining good performance.

Abstract: A power amplifier utilizes cascode arrangements to achieve target performance levels for a power amplifier, such as the type used in wireless communication devices. A negative resistance circuit is provided for the cascode arrangement such that high gain, or oscillation, is promoted during operation of the power amplifier. In one embodiment, the negative resistance circuit includes cross-coupling transistors. Various features are provided in order to reduce the susceptibility of the power amplifier to voltage breakdown while maintaining good performance.

Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.

Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.

Abstract: An integrated inductive element may be formed over a substrate. A triple well may be defined in a star-shape, in one embodiment, in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic coupling between integrated inductors associated with the same integrated circuit.

Abstract: An integrated inductive element may be formed over a substrate. A triple well may be defined in a star-shape, in one embodiment, in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic coupling between integrated inductors associated with the same integrated circuit.