Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive lines in a dielectric layer, individual ones of the plurality of conductive lines along a direction and spaced at a same interval. A conductive structure is in the dielectric layer, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer. The conductive feedthrough structure is a monolithic structure extending through the device layer.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.

Abstract: Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive structures along corresponding ones of a plurality of line tracks along a first direction. The integrated circuit structure also includes a white space track included within the plurality of line tracks, the white space track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction. A conductive structure is along the white space track.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.