Patents by Inventor Clifton G. Fonstad, Jr.

Clifton G. Fonstad, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140328362
    Abstract: Described herein is a novel technique used to make novel thin III-V semiconductor cleaved facet edge emitting active optical devices, such as lasers and optical amplifiers. These fully processed laser platelets with both top side and bottom side electrical contacts can be thought of as freestanding optoelectronic building blocks that can be integrated as desired on diverse substrates for a number of applications, many of which are in the field of communications. The thinness of these platelets and the precision with which their dimensions are defined using the process described herein makes it conducive to assemble them in dielectric recesses on a substrate, such as silicon, as part of an end-fire coupled, coaxial alignment optoelectronic integration strategy. This technology has been used to integrate edge emitting lasers onto silicon substrates, a significant challenge in the field of silicon optoelectronics.
    Type: Application
    Filed: February 22, 2013
    Publication date: November 6, 2014
    Inventors: Joseph John Rumpler, Clifton G. Fonstad, JR.
  • Patent number: 8409888
    Abstract: Described herein is a novel technique used to make novel thin III-V semiconductor cleaved facet edge emitting active optical devices, such as lasers and optical amplifiers. These fully processed laser platelets with both top side and bottom side electrical contacts can be thought of as freestanding optoelectronic building blocks that can be integrated as desired on diverse substrates for a number of applications, many of which are in the field of communications. The thinness of these platelets and the precision with which their dimensions are defined using the process described herein makes it conducive to assemble them in dielectric recesses on a substrate, such as silicon, as part of an end-fire coupled, coaxial alignment optoelectronic integration strategy. This technology has been used to integrate edge emitting lasers onto silicon substrates, a significant challenge in the field of silicon optoelectronics.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 2, 2013
    Inventors: Joseph John Rumpler, Clifton G. Fonstad, Jr.
  • Patent number: 7956382
    Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: June 7, 2011
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Markus Zahn
  • Patent number: 7323757
    Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: January 29, 2008
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Markus Zahn
  • Patent number: 6888178
    Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: May 3, 2005
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Markus Zahn
  • Patent number: 6833277
    Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 21, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Markus Zahn
  • Patent number: 6825049
    Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: November 30, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Markus Zahn
  • Patent number: 6455398
    Abstract: In a method for bonding a silicon substrate to a III-V material substrate, a silicon substrate is contacted together with a III-V material substrate and the contacted substrates are annealed at a first temperature that is above ambient temperature, e.g., at a temperature of between about 150° C. and about 350° C. The silicon substrate is then thinned. This bonding process enables the fabrication of thick, strain-sensitive and defect-sensitive optoelectronic devices on the optimum substrate for such, namely, a thick III-V material substrate, while enabling the fabrication of silicon electronic devices in a thin silicon layer, resulting from the thinned Si substrate, that is sufficient for such fabrication but which has been thinned to eliminate thermally-induced stress in both the Si and III-V materials. The III-V material substrate thickness thereby provides the physical strength of the composite substrate structure, while the thinned silicon substrate minimizes stress in the composite structure.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: September 24, 2002
    Assignee: Massachusetts Institute of Technology
    Inventors: Clifton G. Fonstad, Jr., Joanna M. London, Joseph F. Ahadian
  • Patent number: 4827482
    Abstract: A method and apparatus for phase-locking semiconductor laser arrays is described wherein individual light waves propagating in adjacent waveguides are phase-locked by intercoupling the waveguides in a specific manner. The waveguides are intercoupled in an unguided mode-mixing region wherein various modes of propagation mix by diffraction. The length of this region is fixed at a distance z which produces a phase difference an integral multiple of 2.pi. between adjacent waveguides.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: May 2, 1989
    Assignee: Massachusetts Institute of Technology
    Inventors: Elias Towe, Clifton G. Fonstad, Jr.
  • Patent number: 4773355
    Abstract: A method and apparatus for forming epitaxial thin film layers on substrates having abrupt transitions between layers of different composition or layers of different or like composition with different degrees of doping included therein. Gaseous reactants containing the desired elements to be included in the first film layer are injected into a CVD reaction chamber containing a substrate. The substrate is heated to a temperature high enough to obtain an epitaxial deposit, but low enough so as not to cause decomposition of the reactants. Once the gaseous reactant flows reach steady-state, an electric discharge or plasma is created in the gases to initiate the decomposition reaction and obtain a deposit. In this way, no transient effects are present. Once the deposit has attained sufficient thickness, the electric discharge is turned off to abruptly terminate deposition.
    Type: Grant
    Filed: December 9, 1986
    Date of Patent: September 27, 1988
    Assignee: Massachusetts Institute of Technology
    Inventors: L. Rafael Reif, Clifton G. Fonstad, Jr.
  • Patent number: 4659401
    Abstract: A method and apparatus for forming epitaxial thin film layers on substrates having abrupt transitions between layers of different composition or layers of different or like composition with different degrees of doping included therein. Gaseous reactants containing the desired elements to be included in the first film layer are injected into a CVD reaction chamber containing a substrate. The substrate is heated to a temperature high enough to obtain an epitaxial deposit, but low enough so as not to cause decomposition of the reactants. Once the gaseous reactant flows reach steady-state, an electric discharge or plasma is created in the gases to initiate the decomposition reaction and obtain a deposit. In this way, no transient effects are present. Once the deposit has attained sufficient thickness, the electric discharge is turned off to abruptly terminate deposition.
    Type: Grant
    Filed: June 10, 1985
    Date of Patent: April 21, 1987
    Assignee: Massachusetts Institute of Technology
    Inventors: L. Rafael Reif, Clifton G. Fonstad, Jr.
  • Patent number: 3953879
    Abstract: A field effect semiconductor device that has particular use in limiting current in electric circuits over a very wide power range. In a preferred form, the device consists of a crystalline-material semiconductor wafer having multiple channels at one major surface thereof, the channels being separated by grooves formed along parallel crystallographic planes of the crystalline material. The wafer material forming each of the channels is lightly doped and each channel is bounded by flat walls, parallel to one another and formed by highly doping the wafer material with a dopant that is opposite in type to that of the channels. All said one major surface of the wafer is highly doped with the opposite-type dopant to that of the channels with the exception of ohmic-electric-contact regions of each channel, which regions are highly doped with the same-type dopant as that of the channels. All said one surface, except at the edge or edges thereof, is covered by a first conductive terminal.
    Type: Grant
    Filed: July 12, 1974
    Date of Patent: April 27, 1976
    Assignee: Massachusetts Institute of Technology
    Inventors: Jorge O'Connor-d'Arlach, Clifton G. Fonstad, Jr.