Patents by Inventor Clinton E. Bubb
Clinton E. Bubb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10936389Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; and executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists.Type: GrantFiled: February 7, 2019Date of Patent: March 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Enrique Aleman, Clinton E. Bubb, Ying-yeung Li, Myron T. Wisniewski
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Patent number: 10346311Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: GrantFiled: November 7, 2017Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190188069Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; and executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists.Type: ApplicationFiled: February 7, 2019Publication date: June 20, 2019Inventors: Enrique Aleman, Clinton E. Bubb, Ying-yeung Li, Myron T. Wisniewski
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Patent number: 10310996Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: GrantFiled: May 31, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Patent number: 10303627Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: GrantFiled: November 2, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Patent number: 10248485Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists; and executing, by the processor, an initialization method for both of the first and second PCHIDs.Type: GrantFiled: December 16, 2016Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Enrique Aleman, Clinton E. Bubb, Ying-yeung Li, Myron T. Wisniewski
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Patent number: 10210095Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: GrantFiled: July 6, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Patent number: 10210106Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.Type: GrantFiled: March 15, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven G. Aden, Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190012269Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: ApplicationFiled: November 7, 2017Publication date: January 10, 2019Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20190012268Abstract: A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20180349299Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Publication number: 20180349300Abstract: A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.Type: ApplicationFiled: November 2, 2017Publication date: December 6, 2018Inventors: Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Kirk Pospesel
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Publication number: 20180267909Abstract: A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.Type: ApplicationFiled: March 15, 2017Publication date: September 20, 2018Inventors: Steven G. Aden, Clinton E. Bubb, Michael Grassi, Howard M. Haynie, Raymond M. Higgs, Luke M. Hopkins, Kirk Pospesel, Gabriel M. Tarr
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Publication number: 20180173582Abstract: Aspects of the present invention include a method, system and computer program product. The method includes a processor operating first and second physical channel identifier (PCHID) devices comprised of a plurality of functional logic components, wherein one or more of the functional logic components are specific to one or more of the first and second PCHIDs and wherein one or more of the functional logic components are in common and not specific to one or more of the first and second PCHIDs; determining that an error condition exists in the first PCHID or the second PCHID; executing a recovery method to remove the error condition from the first PCHID or the second PCHID in which the error condition exists; and executing, by the processor, an initialization method for both of the first and second PCHIDs.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Enrique Aleman, Clinton E. Bubb, Ying-yeung Li, Myron T. Wisniewski
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Patent number: 9792167Abstract: Examples of techniques for transparent north port recovery of an error in an input/output device are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processing device, a command timeout; sending, by the processing device, an input/output (I/O) error signal to a host processing system connected to the hardware device via a north port of the hardware device; terminating, by the host processing system, a link between the north port of the hardware device and the host processing system; enabling, by the processing device, halt command forwarding on the hardware device; halting, by the processing device, commands upon detecting the halt command forwarding; and resetting, by the processing device, the link between the north port of the hardware device and the host processing system.Type: GrantFiled: September 27, 2016Date of Patent: October 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael J. Becht, Clinton E. Bubb, Jeffrey C. Hanscom, Andreas Kohler, Ying-Yeung Li, Mushfiq U. Saleheen, Raymond Wong, Jie Zheng
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Patent number: 9727756Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.Type: GrantFiled: September 1, 2016Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Andrew R. Ranck
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Patent number: 9619674Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.Type: GrantFiled: December 12, 2014Date of Patent: April 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Andrew R. Ranck
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Patent number: 9569391Abstract: Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.Type: GrantFiled: May 23, 2014Date of Patent: February 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Daniel F. Casper, John R. Flanagan, Raymond M. Higgs, George P. Kuch, Jeffrey M. Turner
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Patent number: 9524403Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.Type: GrantFiled: April 5, 2016Date of Patent: December 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Clinton E. Bubb, Andrew R. Ranck
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Publication number: 20160364361Abstract: A method, computer program product, and system to implement access control from a master device to a slave device over an inter-integrated circuit (I2C) interface are described. The method includes generating, using a processor, a control block defining the access control to the slave device over the I2C interface. The generating the control block is performed by the trusted code layer and the generating the control block is prohibited by the user-modifiable code layer. The method also includes controlling a command over the I2C interface to the slave device based on a generated command from the trusted code layer and the user-modifiable code layer in accordance with the control block.Type: ApplicationFiled: September 1, 2016Publication date: December 15, 2016Inventors: Clinton E. Bubb, Andrew R. Ranck