Patents by Inventor Coen TAK

Coen TAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230126598
    Abstract: In an embodiment, a semiconductor package includes a support and a stack of two or more semiconductor dies, the stack including an upper die and further including a lower die attached to the support by adhesive on a backside of the lower die, wherein the adhesive covers only part of the backside of the lower die, and wherein the adhesive has a plurality of non-contiguous regions on the backside of the lower die.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 27, 2023
    Inventors: Casper Van Der Avoort, Willem Besling, Remco Pijinenburg, Olaf Wunnicke, Coen Tak
  • Patent number: 11548781
    Abstract: A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 10, 2023
    Assignee: SCIOSENSE B.V.
    Inventors: Casper Van Der Avoort, Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Coen Tak
  • Publication number: 20210273401
    Abstract: The disclosure describes packages having portions of a lead frame as electrically conductive leads. The conductive leads can facilitate bringing signals acquired at the top of a package down to electrically conductive pads at the bottom of the package (or vice-versa). The techniques can be used in a range of different applications, for example, the monitoring of signals to enhance the safety of a light emitting package, as well as other applications in which a signal acquired at a top side of an package needs to be brought to conductive pads at a bottom side of the package, or to bring signals from conductive pads at the bottom side of the package to the top side of the package.
    Type: Application
    Filed: July 12, 2019
    Publication date: September 2, 2021
    Inventors: Martin Lukas Balimann, Harald Etschmaier, Coen Tak, Ian Kilburn, Arnold Umali
  • Publication number: 20200361764
    Abstract: A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.
    Type: Application
    Filed: November 16, 2018
    Publication date: November 19, 2020
    Inventors: Casper Van Der Avoort, Willem Frederik Adrianus Besling, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Coen Tak
  • Patent number: 9034493
    Abstract: Consistent with an example embodiment, there is an apparatus comprising a carrier, a laminated battery provided on a major surface of the carrier, and an integrated circuit. The laminated battery includes a bottom electrode layer, an electrolyte layer, and a top electrode layer. The integrated circuit is connected to the bottom electrode layer and the top electrode layer. The integrated circuit is surrounded by the laminated battery on the major surface of the carrier.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: May 19, 2015
    Assignee: NXP B.V.
    Inventors: Romano Hoofman, Coen Tak, Marc Andre De Samber
  • Publication number: 20110293969
    Abstract: Consistent with an example embodiment, there is an apparatus comprising a carrier, a laminated battery provided on a major surface of the carrier, and an integrated circuit. The laminated battery includes a bottom electrode layer, an electrolyte layer, and a top electrode layer. The integrated circuit is connected to the bottom electrode layer and the top electrode layer. The integrated circuit is surrounded by the laminated battery on the major surface of the carrier.
    Type: Application
    Filed: November 24, 2010
    Publication date: December 1, 2011
    Applicant: NXP B.V.
    Inventors: Romano HOOFMAN, Coen TAK, Marc Andre de SAMBER