Patents by Inventor Coenraad Cornelis Tak

Coenraad Cornelis Tak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664447
    Abstract: A semiconductor device and a method of making the same. The device includes a substrate mounted on a carrier, the substrate comprising a High Electron Mobility Transistor (HEMT) having a source, a gate and a drain. The carrier comprises an electrically conductive shielding portion for providing shielding against electromagnetic interference associated with switching of the device during operation. The electrically conductive shielding portion is electrically isolated from the source and from the backside of the substrate.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 30, 2023
    Assignee: Nexperia B.V.
    Inventors: Jeroen Croon, Coenraad Cornelis Tak
  • Publication number: 20220260446
    Abstract: In an embodiment a sensor arrangement includes a sensor die having a contact area, a suspended area and a sensitive element located in the suspended area, an interposer including at least two vias connecting a first side of the interposer to a second side of the interposer and a support mechanically and electrically connecting the contact area of the sensor die to the first side of the interposer, the support including at least two contact joints.
    Type: Application
    Filed: July 22, 2020
    Publication date: August 18, 2022
    Inventors: Willem Frederik Adrianus Besling, Anderson Pires Singulani, Coenraad Cornelis Tak, Casper Van Der Avoort
  • Publication number: 20220221363
    Abstract: In an embodiment a method for forming a pressure sensor device includes providing a pressure sensor on a substrate body, the pressure sensor comprising a membrane, depositing a top layer on top of the substrate body and the pressure sensor, connecting a cap body with the top layer, a mass of the cap body being approximately equal to a mass of the substrate body and introducing at least one opening in the cap body.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: Jörg Siegert, Willem Frederik Adrianus Besling, Coenraad Cornelis Tak, Martin Schrems, Franz Schrank
  • Patent number: 11366031
    Abstract: In an embodiment, a semiconductor device includes a substrate body, an environmental sensor, a cap body and a volume of gas, wherein the environmental sensor and the volume of gas are arranged between the substrate body and the cap body in a vertical direction which is perpendicular to a main plane of extension of the substrate body, wherein at least one channel between the substrate body and the cap body connects the volume of gas with an environment of the semiconductor device such that the channel is permeable for gases, and wherein a thickness of the substrate body amounts to at least 80% of a thickness of the cap body and at most 120% of the thickness of the cap body.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 21, 2022
    Assignee: SCIOSENSE B.V.
    Inventors: Willem Frederik Adrianus Besling, Casper Van Der Avoort, Coenraad Cornelis Tak, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Martijn Goossens
  • Patent number: 11313749
    Abstract: In an embodiment a pressure sensor device includes a substrate body, a pressure sensor having a membrane and a cap body having at least one opening, wherein the pressure sensor is arranged between the substrate body and the cap body in a vertical direction which is perpendicular to a main plane of extension of the substrate body, and wherein the mass of the substrate body amounts to at least 80% of the mass of the cap body and at most 120% of the mass of the cap body.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 26, 2022
    Assignee: SCIOSENSE B.V.
    Inventors: Joerg Siegert, Willem Frederik Adrianus Besling, Coenraad Cornelis Tak, Martin Schrems, Franz Schrank
  • Publication number: 20210229981
    Abstract: A sensor package and a method for producing a sensor package are disclosed. In an embodiment a method for producing a sensor package includes providing a carrier including electric conductors, fastening a dummy die or interposer to the carrier, providing an ASIC device including an integrated sensor element and fastening the ASIC device to the dummy die or interposer.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Willem Frederik Adrianus Besling, Casper Van Der Avoort, Coenraad Cornelis Tak, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Hendrik Bouman
  • Patent number: 11001495
    Abstract: The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: May 11, 2021
    Assignee: Sciosense B.V.
    Inventors: Willem Frederik Adrianus Besling, Casper Van Der Avoort, Coenraad Cornelis Tak, Remco Henricus Wilhelmus Pijnenburg, Olaf Wunnicke, Hendrik Bouman
  • Publication number: 20190375628
    Abstract: The sensor package comprises a carrier (1) including electric conductors (13), an ASIC device (6) and a sensor element (7), which is integrated in the ASIC device (6). A dummy die or interposer (4) is arranged between the carrier (1) and the ASIC device (6). The dummy die or interposer (4) is fastened to the carrier (1), and the ASIC device (6) is fastened to the dummy die or interposer (4).
    Type: Application
    Filed: June 14, 2017
    Publication date: December 12, 2019
    Applicant: ams International AG
    Inventors: Willem Frederik Adrianus BESLING, Casper van der AVOORT, Coenraad Cornelis TAK, Remco Henricus Wilhelmus PIJNENBURG, Olaf WUNNICKE, Hendrik BOUMAN
  • Publication number: 20190265119
    Abstract: A pressure sensor device comprises a substrate body, a pressure sensor comprising a membrane, and a cap body comprising at least one opening. The pressure sensor is arranged between the substrate body and the cap body in a vertical direction which is perpendicular to the main plane of extension of the substrate body, and the mass of the substrate body equals approximately the mass of the cap body. Furthermore, a method for forming a pressure sensor device is provided.
    Type: Application
    Filed: October 2, 2017
    Publication date: August 29, 2019
    Inventors: Joerg Siegert, Willem Frederik Adrianus Besling, Coenraad Cornelis Tak, Martin SCHREMS, FRANZ SCHRANK
  • Publication number: 20190234821
    Abstract: A semiconductor device comprises a substrate body, an environmental sensor, a cap body and a volume of gas. The environmental sensor and the volume of gas are arranged between the substrate body and the cap body in a vertical direction which is perpendicular to the main plane of extension of the substrate body, and at least one channel between the substrate body and the cap body connects the volume of gas with the environment of the semiconductor device such that the channel is permeable for gases.
    Type: Application
    Filed: October 2, 2017
    Publication date: August 1, 2019
    Inventors: Willem Frederik Adrianus BESLING, Casper VAN DER AVOORT, Coenraad Cornelis TAK, Remco Henricus Wilhelmus PIJNENBURG, Olaf WUNNICKE, Martijn GOOSSENS
  • Patent number: 9666637
    Abstract: Disclosed is an integrated sensor chip package comprising an integrated sensor chip enveloped in a packaging layer (30), the integrated circuit comprising a substrate (10) having a major surface; and a light sensor comprising a plurality of photodetectors (12a-d) on a region of said major surface; the packaging layer comprising an opening (32) exposing said region, the integrated sensor chip package further comprising a light blocking member (20) over said opening, the light blocking member defining an aperture (22) exposing a first set of photodetectors to light from a first range of directions and exposing a second set of photodetectors to light from a second range of directions, wherein the first range is different to the second range. An apparatus including such an integrated sensor chip package and a method of manufacturing such an integrated sensor chip package are also disclosed.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 30, 2017
    Assignee: NXP B.V.
    Inventors: Zoran Zivkovic, Coenraad Cornelis Tak
  • Publication number: 20170133303
    Abstract: A semiconductor device and a method of making the same. The device includes a substrate mounted on a carrier, the substrate comprising a High Electron Mobility Transistor (HEMT) having a source, a gate and a drain. The carrier comprises an electrically conductive shielding portion for providing shielding against electromagnetic interference associated with switching of the device during operation. The electrically conductive shielding portion is electrically isolated from the source and from the backside of the substrate.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 11, 2017
    Inventors: Jeroen Croon, Coenraad Cornelis Tak
  • Patent number: 9461002
    Abstract: A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 4, 2016
    Assignee: NXP B.V.
    Inventors: Jeroen Antoon Croon, Coenraad Cornelis Tak
  • Patent number: 9385099
    Abstract: One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: July 5, 2016
    Assignee: NXP, B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Coenraad Cornelis Tak, Marten Oldsen, Hendrik Bouman
  • Publication number: 20160163653
    Abstract: A semiconductor device and a method of making the same. The semiconductor device includes a semiconductor substrate mounted on a carrier. The semiconductor substrate includes a Schottky diode. The Schottky diode has an anode and a cathode. The semiconductor device also includes one or more bond wires connecting the cathode to a first electrically conductive portion of the carrier. The semiconductor device further includes one or more bond wires connecting the anode to a second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is electrically isolated from the second electrically conductive portion of the carrier. The first electrically conductive portion of the carrier is configured to provide shielding against electromagnetic interference associated with switching of the anode during operation of the device.
    Type: Application
    Filed: October 2, 2015
    Publication date: June 9, 2016
    Inventors: Jeroen Antoon Croon, Coenraad Cornelis Tak
  • Patent number: 9177852
    Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: November 3, 2015
    Assignee: NXP B.V.
    Inventors: Peter Gerard Steeneken, Roel Daamen, Gerard Koops, Jan Sonsky, Evelyne Gridelet, Coenraad Cornelis Tak
  • Publication number: 20150279803
    Abstract: One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: NXP B.V.
    Inventors: Leonardus Antonius Elisabeth van Gemert, Coenraad Cornelis Tak, Marten Oldsen, Hendrik Bouman
  • Patent number: 9070695
    Abstract: An integrated circuit package for an integrated circuit having one or more sensor elements in a sensor element area of the circuit. An encapsulation covers bond wires but leaves an opening over the sensor element area. A protection layer is provided over the integrated circuit over which the encapsulation extends, and it has a channel around the sensor element area to act as a trap for any encapsulation material which has crept into the opening area.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 30, 2015
    Assignee: NXP, B.V.
    Inventors: Roel Daamen, Hendrik Bouman, Coenraad Cornelis Tak
  • Publication number: 20140361394
    Abstract: Disclosed is an integrated sensor chip package comprising an integrated sensor chip enveloped in a packaging layer (30), the integrated circuit comprising a substrate (10) having a major surface; and a light sensor comprising a plurality of photodetectors (12a-d) on a region of said major surface; the packaging layer comprising an opening (32) exposing said region, the integrated sensor chip package further comprising a light blocking member (20) over said opening, the light blocking member defining an aperture (22) exposing a first set of photodetectors to light from a first range of directions and exposing a second set of photodetectors to light from a second range of directions, wherein the first range is different to the second range. An apparatus including such an integrated sensor chip package and a method of manufacturing such an integrated sensor chip package are also disclosed.
    Type: Application
    Filed: June 9, 2014
    Publication date: December 11, 2014
    Applicant: NXP B.V.
    Inventors: Zoran Zivkovic, Coenraad Cornelis Tak
  • Publication number: 20140342527
    Abstract: An isolated semiconductor circuit comprising: a first sub-circuit and a second sub-circuit; a backend that includes an electrically isolating connector between the first and second sub-circuits; a lateral isolating trench between the semiconductor portions of the first and second sub-circuits, wherein the lateral isolating trench extends along the width of the semiconductor portions of the first and second sub-circuits, wherein one end of the isolating trench is adjacent the backend, and wherein the isolating trench is filled with an electrically isolating material.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Peter Gerard STEENEKEN, Roel DAAMEN, Gerard KOOPS, Jan SONSKY, Evelyne GRIDELET, Coenraad Cornelis TAK