Patents by Inventor Coke S. Reed
Coke S. Reed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210112019Abstract: Embodiments of an interconnect apparatus advantageously useful in handling Big Data Graph Analytics enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array.Type: ApplicationFiled: November 12, 2020Publication date: April 15, 2021Applicant: Interactic Holding, LLCInventors: Coke S. Reed, David Murphy, Ronald R. Denny, Michael R. Ives, Reed Devany
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Patent number: 10893003Abstract: Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. Since the Data Vortex switches are not crossbar switches, there is no need to globally set and reset the Data Vortex switches as different groups of packets enter the switches.Type: GrantFiled: December 12, 2019Date of Patent: January 12, 2021Inventors: Coke S. Reed, David Murphy, Ronald R. Denny, Michael R. Ives, Reed Devany
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Publication number: 20200195584Abstract: Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. Since the Data Vortex switches are not crossbar switches, there is no need to globally set and reset the Data Vortex switches as different groups of packets enter the switches.Type: ApplicationFiled: December 12, 2019Publication date: June 18, 2020Applicant: Interactic Holding, LLCInventors: Coke S. Reed, David Murphy, Ronald R. Denny, Michael R. Ives, Reed Devany
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Patent number: 10630607Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: GrantFiled: April 23, 2018Date of Patent: April 21, 2020Assignee: Interactic Holdings, LLCInventors: Coke S. Reed, David Murphy
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Publication number: 20180241694Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Inventors: Coke S. Reed, David Murphy
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Patent number: 9954797Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: GrantFiled: March 17, 2017Date of Patent: April 24, 2018Assignee: Interactic Holdings, LLCInventors: Coke S. Reed, David Murphy
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Patent number: 9930117Abstract: Techniques are disclosed relating to parallel computing. In some embodiments, fine-grained data communication facilitates operations on large data sets such as multiplication of a sparse matrix by a vector. In this example, a first data set (the matrix) and a second data set (the vector) are distributed across multiple processing nodes. Performance of the overall multiplication operation may require communication of data among the processing nodes. In various embodiments, fine-grained communication of this data may reduce processing times and/or power consumption by avoiding congestion.Type: GrantFiled: September 30, 2015Date of Patent: March 27, 2018Assignee: Interactic Holdings, LLCInventors: Coke S. Reed, Ronald R. Denny, Jay W. Rockstroh, Michael R. Ives
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Publication number: 20170195252Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: ApplicationFiled: March 17, 2017Publication date: July 6, 2017Inventors: Coke S. Reed, David Murphy
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Patent number: 9634862Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: GrantFiled: July 30, 2014Date of Patent: April 25, 2017Assignee: INTERACTIC HOLDINGS, LLCInventors: Coke S Reed, David Murphy
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Patent number: 9479458Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: GrantFiled: March 25, 2011Date of Patent: October 25, 2016Inventors: Coke S. Reed, David Murphy
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Publication number: 20160105494Abstract: Techniques are disclosed relating to performing Fast Fourier Transforms (FFTs) using distributed processing. In some embodiments, results of local transforms that are performed in parallel by networked processing nodes are scattered across processing nodes in the network and then aggregated. This may transpose the local transforms and store data in the correct placement for performing further local transforms to generate a final FFT result. The disclosed techniques may allow latency of the scattering and aggregating to be hidden behind processing time, in various embodiments, which may greatly reduce the time taken to perform FFT operations on large input data sets.Type: ApplicationFiled: October 8, 2015Publication date: April 14, 2016Inventors: Coke S. Reed, Ronald R. Denny, Michael R. Ives, Terence J. Donnelly
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Publication number: 20160094660Abstract: Techniques are disclosed relating to parallel computing. In some embodiments, fine-grained data communication facilitates operations on large data sets such as multiplication of a sparse matrix by a vector. In this example, a first data set (the matrix) and a second data set (the vector) are distributed across multiple processing nodes. Performance of the overall multiplication operation may require communication of data among the processing nodes. In various embodiments, fine-grained communication of this data may reduce processing times and/or power consumption by avoiding congestion.Type: ApplicationFiled: September 30, 2015Publication date: March 31, 2016Inventors: Coke S. Reed, Ronald R. Denny, Jay W. Rockstroh, Michael R. Ives
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Patent number: 9253248Abstract: Embodiments of a data handling apparatus can include a network interface controller configured to interface a processing node to a network. The network interface controller can include a network interface, a register interface, a processing node interface, and logic. The network interface can include lines coupled to the network for communicating data on the network. The register interface can include lines coupled to multiple registers. The processing node interface can include at least one line coupled to the processing node for communicating data with a local processor local to the processing node wherein the local processor can read data to and write data from the registers. The logic can receive packets including a header and a payload from the network and can insert the packets into the registers as indicated by the header.Type: GrantFiled: November 15, 2011Date of Patent: February 2, 2016Assignee: Interactic Holdings, LLCInventors: Coke S. Reed, Ron Denny, Michael Ives, Thaine Hock
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Publication number: 20150188987Abstract: Embodiments of a data handling apparatus can include a network interface controller configured to interface a processing node to a network. The network interface controller can include a network interface, a register interface, a processing node interface, and logic. The network interface can include lines coupled to the network for communicating data on the network. The register interface can include lines coupled to multiple registers. The processing node interface can include at least one line coupled to the processing node for communicating data with a local processor local to the processing node wherein the local processor can read data to and write data from the registers. The logic can receive packets including a header and a payload from the network and can insert the packets into the registers as indicated by the header.Type: ApplicationFiled: November 15, 2011Publication date: July 2, 2015Inventors: COKE S. REED, RON DENNY, MICHAEL IVES, THAINE HOCK
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Publication number: 20150023367Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: ApplicationFiled: March 25, 2011Publication date: January 22, 2015Inventors: Coke S. Reed, David Murphy
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Publication number: 20140341077Abstract: An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD.Type: ApplicationFiled: July 30, 2014Publication date: November 20, 2014Inventors: Coke S. Reed, David Murphy
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Patent number: 8874797Abstract: A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.Type: GrantFiled: January 17, 2012Date of Patent: October 28, 2014Assignee: Interactic Holding, LLCInventor: Coke S. Reed
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Patent number: 8825896Abstract: In a system, a memory controller separates a memory into multiple banks and enables a plurality of selected banks to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.Type: GrantFiled: June 10, 2004Date of Patent: September 2, 2014Assignee: Interactic Holdings, Inc.Inventors: Coke S. Reed, David Murphy
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Publication number: 20120185614Abstract: A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.Type: ApplicationFiled: January 17, 2012Publication date: July 19, 2012Inventor: Coke S. Reed
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Patent number: 8099521Abstract: A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.Type: GrantFiled: October 26, 2007Date of Patent: January 17, 2012Assignee: Interactic Holdings Inc.Inventor: Coke S. Reed