Abstract: An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: A memory cell made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an active low conductive layer and passive layer. The controllably conductive media changes its impedance when an external stimuli such as an applied electric field is imposed thereon. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: An organic memory cell made of two electrodes with a selectively conductive media between the two electrodes is disclosed. The selectively conductive media contains an organic layer and passive layer. The selectively conductive media is programmed by applying bias voltages that program a desired impedance state for a memory cell. The desired impedance state represents one or more bits of information and the memory cell does not require constant power or refresh cycles to maintain the desired impedance state. Furthermore, the selectively conductive media is read by applying a current and reading the impedance of the media in order to determine the impedance state of the memory cell. Methods of making the organic memory devices/cells, methods of using the organic memory devices/cells, and devices such as computers containing the organic memory devices/cells are also disclosed.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: For generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a voltage regulator and a charge pump fabricated on the semiconductor wafer, and the low voltage source is the ground node. In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node.

Abstract: In a BIST (built-in-self-test) interface, a serial shift register, fabricated on the semiconductor die having an array of core flash memory cells fabricated thereon, inputs test type data from an external test system via first IO1 and second IO2 pins, during a first state. A test type decoder, fabricated on the semiconductor die, decodes the test type data to determine whether a built-in-self-test mode is invoked by the external test system. A third portion of the serial shift register serially inputs test mode data from the external test system via the first IO1 pin, and the test mode data defines a set of desired test modes to be performed on the array of core flash memory cells. A front-end state machine, fabricated on the semiconductor die, decodes the test mode data to determine an order for performing the desired test modes.

Abstract: In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.

Abstract: A method for serial sequencing the automatic disturb erase verify (APDEV) function during a multiple sector fast erase mode. The fast erase mode allows a memory device to erase several sectors of memory cells simultaneously. In order to minimize the time required to complete the APDEV and APDE functions, latches store for the address lines of the sector column positions. The APDEV function, therefore, can be performed serially on each of the sectors in the multiple sector group instead of all the sectors in the group simultaneously, thereby decreasing the amount of time required for the APDEV and APDE functions during the fast erase mode.

Abstract: A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated.

Abstract: A method for sensing the state of erasure of a flash (EEPROM) memory device. In one embodiment, the source voltage during erase is monitored and compared to a value determined during a characterization procedure. In a second embodiment, the rate of change of the source voltage during erase is determined and compared to a value determined during a characterization procedure. The characterization procedure correlates state of erasure with source voltages and slopes of the rate of change of source voltage versus time curve for the memory cells. The determination of the source voltage and the determination of the rate of change of the source voltage and the associated state of erasure allows modification of the erase procedure.

Abstract: A method of erase verifying and overerase verifying an array of flash memory cells by erase verifying each memory cell bit-by-bit in a memory array, overerase verifying each memory cell bit-by-bit in the memory array after each memory cell verifies as erased and again erase verifying each memory cell bit-by-bit in the memory array after each cell overerase verifies. The threshold voltage of each memory cell is compared to the threshold voltage of a reference memory cell and an overerase correction pulse is applied to the column in which the overerased memory cell is located.

Abstract: A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.

Abstract: The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.

Abstract: An improved reading structure (110) for performing a read operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells, each being previously programmed to one of a plurality of memory conditions defined by memory core threshold voltages. A reference cell array (22) includes a plurality of reference core cells which are selected together with a selected core cell and provides selectively one of a plurality of reference cell bit line voltages defined by reference cell threshold voltages. Each of the reference cells are previously programmed at the same time as when the memory core cells are being programmed. A precharge circuit (36) is used to precharge the array bit lines and the reference bit lines to a predetermined potential. A detector circuit (28) is responsive to the bit line voltages of the reference cells for generating strobe signals.