Patents by Inventor Colin Christopher Sharp
Colin Christopher Sharp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10282813Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.Type: GrantFiled: February 13, 2018Date of Patent: May 7, 2019Assignee: QUALCOMM IncorporatedInventors: Murat Balci, Avinash Seetharamaiah, Christopher Paul Frascati, Jonnala Gadda Nagendra Kumar, Colin Christopher Sharp, David Rigel Garcia Garcia
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Patent number: 10102391Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to an unsecure memory unit or a secure memory unit based on the unsecure mode or secure mode and a resource descriptor associated with a memory resource.Type: GrantFiled: August 7, 2015Date of Patent: October 16, 2018Assignee: QUALCOMM IncorporatedInventors: Colin Christopher Sharp, Ramesh Viswanathan
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Patent number: 10002021Abstract: This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.Type: GrantFiled: July 20, 2012Date of Patent: June 19, 2018Assignee: QUALCOMM IncorporatedInventors: Eduardus A Metz, Nigel Terence Poole, Colin Christopher Sharp, Andrew Gruber
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Publication number: 20180165788Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.Type: ApplicationFiled: February 13, 2018Publication date: June 14, 2018Inventors: Murat Balci, Avinash Seetharamaiah, Christopher Paul Frascati, Jonnala Gadda Nagendra Kumar, Colin Christopher Sharp, David Rigel Garcia Garcia
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Patent number: 9928565Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.Type: GrantFiled: April 20, 2015Date of Patent: March 27, 2018Assignee: QUALCOMM IncorporatedInventors: Murat Balci, Avinash Seetharamaiah, Christopher Paul Frascati, Jonnala gadda Nagendra Kumar, Colin Christopher Sharp, David Rigel Garcia Garcia
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Publication number: 20180040095Abstract: This disclosure describes techniques for compressing a graphical state object. In one example, a central processing unit may be configured to receive, for output to the GPU, a set of instructions to render a scene. Responsive to receiving the set of instructions to render the scene, the central processing unit may be further configured to determine whether the set of instructions includes a state object that is registered as corresponding to an identifier. Responsive to determining that the set of instructions includes the state object that is registered as corresponding to the identifier, the central processing unit may be further configured to output, to the GPU, the identifier that is registered as corresponding to the state object.Type: ApplicationFiled: August 2, 2016Publication date: February 8, 2018Inventors: Avinash Seetharamaiah, Christopher Paul Frascati, Jonnala Gadda Nagendra Kumar, Andrew Evan Gruber, Colin Christopher Sharp, Eric Demers
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Patent number: 9779471Abstract: A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.Type: GrantFiled: October 1, 2014Date of Patent: October 3, 2017Assignee: QUALCOMM IncorporatedInventors: Sudeep Ravi Kottilingal, Moinul Khan, Colin Christopher Sharp
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Patent number: 9767320Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to a secure context bank in a memory controller when the GPU is operating in a secure mode, and configured to direct memory transactions from the at least one hardware unit of the GPU to an unsecure context bank in the memory controller when the GPU is operating in the unsecure mode.Type: GrantFiled: August 7, 2015Date of Patent: September 19, 2017Assignee: QUALCOMM IncorporatedInventors: Colin Christopher Sharp, Ramesh Viswanathan
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Patent number: 9645866Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.Type: GrantFiled: September 16, 2011Date of Patent: May 9, 2017Assignee: QUALCOMM IncorporatedInventors: Alexei V. Bourd, Colin Christopher Sharp, David Rigel Garcia Garcia, Chihong Zhang
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Patent number: 9626234Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.Type: GrantFiled: December 15, 2014Date of Patent: April 18, 2017Assignee: QUALCOMM IncorporatedInventors: Alexei Vladimirovich Bourd, Colin Christopher Sharp, David Rigel Garcia Garcia, Chihong Zhang
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Publication number: 20170039381Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to an unsecure memory unit or a secure memory unit based on the unsecure mode or secure mode and a resource descriptor associated with a memory resource.Type: ApplicationFiled: August 7, 2015Publication date: February 9, 2017Inventors: Colin Christopher Sharp, Ramesh Viswanathan
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Publication number: 20170039396Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a memory according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to direct memory transactions from at least one hardware unit of the GPU to a secure context bank in a memory controller when the GPU is operating in a secure mode, and configured to direct memory transactions from the at least one hardware unit of the GPU to an unsecure context bank in the memory controller when the GPU is operating in the unsecure mode.Type: ApplicationFiled: August 7, 2015Publication date: February 9, 2017Inventors: Colin Christopher Sharp, Ramesh Viswanathan
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Patent number: 9489313Abstract: The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.Type: GrantFiled: September 24, 2013Date of Patent: November 8, 2016Assignee: QUALCOMM IncorporatedInventors: David A. Gotwalt, Thomas Edwin Frisinger, Andrew Evan Gruber, Eric Demers, Colin Christopher Sharp
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Patent number: 9436616Abstract: A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.Type: GrantFiled: May 6, 2013Date of Patent: September 6, 2016Assignee: QUALCOMM IncorporatedInventors: Colin Christopher Sharp, Thomas Andrew Sartorius
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Publication number: 20160098813Abstract: A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: Sudeep Ravi Kottilingal, Moinul Khan, Colin Christopher Sharp
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Patent number: 9275429Abstract: The techniques described in the disclosure are generally related to gradual, iterative hang recovery for a graphics processing unit (GPU). The techniques described in the disclosure attempt to re-execute instructions of an application in response to a GPU hang, rather than stopping the execution of the application. If the re-execution causes the GPU to hang again, the techniques described in the disclosure cause the GPU to iteratively execute next set of instructions.Type: GrantFiled: February 17, 2014Date of Patent: March 1, 2016Assignee: QUALCOMM IncorporatedInventors: Srihari Babu Alla, Tarun Reddy Karra, Jonathan Gerald Thomason, Colin Christopher Sharp
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Patent number: 9218289Abstract: A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.Type: GrantFiled: August 2, 2013Date of Patent: December 22, 2015Assignee: QUALCOMM IncorporatedInventors: Bohuslav Rychlik, Tzung Ren Tzeng, Andrew Evan Gruber, Alexei V. Bourd, Colin Christopher Sharp, Eric Demers
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Publication number: 20150302546Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.Type: ApplicationFiled: April 20, 2015Publication date: October 22, 2015Inventors: Murat Balci, Avinash Seetharamaiah, Christopher Paul Frascati, Jonnala gadda Nagendra Kumar, Colin Christopher Sharp, David Rigel Garcia Garcia
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Patent number: 9134954Abstract: This disclosure proposes techniques for demand paging for an IO device (e.g., a GPU) that utilize pre-fetch and pre-back notification event signaling to reduce latency associated with demand paging. Page faults are limited by performing the demand paging operations prior to the IO device actually requesting unbacked memory.Type: GrantFiled: September 10, 2012Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Colin Christopher Sharp, David Rigel Garcia Garcia, Eduardus A. Metz
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Publication number: 20150235338Abstract: The techniques described in the disclosure are generally related to gradual, iterative hang recovery for a graphics processing unit (GPU). The techniques described in the disclosure attempt to re-execute instructions of an application in response to a GPU hang, rather than stopping the execution of the application. If the re-execution causes the GPU to hang again, the techniques described in the disclosure cause the GPU to iteratively execute next set of instructions.Type: ApplicationFiled: February 17, 2014Publication date: August 20, 2015Applicant: QUALCOMM IncorporatedInventors: Srihari Babu Alla, Tarun Karra, Jonathan Gerald Thomason, Colin Christopher Sharp