Abstract: A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Abstract: A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit. A first primary alignment structure is formed in a first position of the inter-layer region around the first mask layer, and a first secondary alignment structure is formed in a second position of the inter-layer region around the first mask layer. Similarly, a second primary alignment structure is formed in a first position of an inter-layer region around the second mask layer, and a second secondary alignment structure is formed in a second position of the inter-layer region around the second mask layer.

Abstract: A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry.

Abstract: A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit. A first primary alignment structure is formed in a first position of the inter-layer region around the first mask layer, and a first secondary alignment structure is formed in a second position of the inter-layer region around the first mask layer. Similarly, a second primary alignment structure is formed in a first position of an inter-layer region around the second mask layer, and a second secondary alignment structure is formed in a second position of the inter-layer region around the second mask layer.

Abstract: The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.