Abstract: A data processor comprises an array of integrated circuits (ICs), each of which comprises an array of data processing elements (PEs) connected to allow transfer of data. The PEs of the data processor may be organized into array-wide rows and columns with data transfer along each row or column. Rows and columns may be subdivided into sections, such division being either intra-chip (all PEs on one IC) or inter-chip (PEs from different ICs), and each section may be arranged for cyclical data transfer within the section. Shift registers with parallel outputs for intra-chip data transfer may be combined with a multiplexer for selecting between parallel data paths and a parallel data output of a local memory for each PE. Similarly, shift registers with serial outputs for inter-chip data tranfer may be combined with a multiplexer for selecting between serial data paths and serial outputs of the shift registers.