Abstract: Radar systems and methods detecting and tracking an unmanned aerial system (UAS) are provided. The radar system and methods can include determining whether or not a UAS is included in the plurality of electromagnetic signals received by the radar system based on one or more expected frequencies that one or more UAS devices use to transmit signals to remote controls. The radar systems and method can also involve switching the radar system into a track mode upon detecting a UAS.

Abstract: A system includes a UV light source and an optical medium coupled to receive UV light from the UV light source. The optical medium is configured to emit UV light proximate to a surface from which biofouling is to be removed once the biofouling has adhered to the protected surface. A method corresponds to the system.

Abstract: A system includes a UV light source and an optical medium coupled to receive UV light from the UV light source. The optical medium is configured to emit UV light proximate to a surface from which biofouling is to be removed once the biofouling has adhered to the protected surface. A method corresponds to the system.

Abstract: A system includes a UV light source and an optical medium coupled to receive UV light from the UV light source. The optical medium is configured to emit UV light proximate to a surface from which biofouling is to be removed once the biofouling has adhered to the protected surface. A method corresponds to the system.

Abstract: A selective frequency limiter having a magnetic material and a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.

Abstract: A selective frequency limiter having a magnetic material and a slow wave structure disposed to magnetically couple a magnetic field, produced by electromagnetic energy propagating through the slow wave structure, into the magnetic material.

Abstract: A system includes a UV light source and an optical medium coupled to receive UV light from the UV light source. The optical medium is configured to emit UV light proximate to a surface from which biofouling is to be removed once the biofouling has adhered to the protected surface. A method corresponds to the system.

Abstract: A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

Abstract: A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Abstract: A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Abstract: A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Abstract: A circuit having: an input matching network; a transistor coupled to an output of the input matching network; and wherein the input matching network has a first input impedance when such input matching network is fed with an input signal having a relatively low power level and wherein the input matching network has an input impedance different from the first input impedance when such input matching network is fed with an input signal having a relatively high power level.

Abstract: A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

Abstract: A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such tarnsistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NH4OH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

Abstract: A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer.

Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Abstract: A method for passivating a III-V material Schottky layer of a field effect transistor. The transistor has a gate electrode in Schottky contact with a gate electrode contact region of the Schottky layer. The gate electrode is adapted to control a flow of carriers between a source electrode of the transistor and a drain electrode of such transistor. The transistor has exposed surface portions of the Schottky layer beween the source electrode and the drain electrode adjacent to the gate electrode contact region of the Schottky layer. The method includes removing organic contamination from the exposed surface portions of the Schottky layer using a oxygen plasma. The contamination removed surface portions of the Schottky layer are exposed to a solution of ammonium sulfide and NH4OH. After removal of the solution, the exposed regions are dried in a nitrogen enviroment. A layer of passivating material is deposited over the dried surface portions.

Abstract: A method is provided for forming a self-aligned, selectively etched, double recess high electron mobility transistor. The method includes providing a semiconductor structure having a III-V substrate; a first relatively wide band gap layer, a channel layer, a second relatively wide band gap Schottky layer, an etch stop layer; a III-V third wide band gap layer on etch stop layer; and an ohmic contact layer on the third relatively wide band gap layer. A mask is provided having a gate contact aperture to expose a gate region of the ohmic contact layer. A first wet chemical etch is brought into contact with portions of the ohmic contact layer exposed by the gate contact aperture. The first wet chemical selectively removes exposed portions of the ohmic contact layer and underlying portions of the third relatively wide band gap layer. The etch stop layer inhibits the first wet chemical etch from removing portions of such etch stop layer.