Patents by Inventor Colin Wai Mun Leong

Colin Wai Mun Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7180377
    Abstract: A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a digital PLL, and a control circuit to control an output oscillator. The control circuit assigns control of the output oscillator between the analog PLL and/or the digital PLL depending on a state of lock of the analog PLL and/or the digital PLL. During a frequency acquisition mode, the digital PLL provides a coarse control of the output oscillator. During a phase capture mode, the analog PLL provides a fine control and the digital PLL provides a coarse control of the output oscillator. During the phase capture mode, the analog PLL control signal and the digital PLL control signal may be given a percentage of control over the output oscillator depending on the state of lock of the analog PLL and/or the digital PLL. During a phase lock mode, the analog PLL controls the output oscillator.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: February 20, 2007
    Assignee: Silicon Clocks Inc.
    Inventors: Colin Wai Mun Leong, Jagdeep Singh Bal, Richard Miller
  • Patent number: 7084709
    Abstract: A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a PLL, and a control circuit to control an output oscillator. The control circuit combines a control signal from the analog PLL with a control signal from the digital PLL to form a composite control signal. The composite control signal is conditioned depending on a state of lock of the analog PLL and/or the digital PLL. The composite signal controls the phase and frequency of the output oscillator. The analog control signal and the digital PLL control signal may be given a percentage of over the hybrid frequency synthesizer depending on the state of lock of the PLL and/or the digital PLL. The composite control signal provides both rapid, accurate, and robust acquisition by the digital PLL, and a smooth transition thereafter to low noise phase lock by the analog PLL.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: August 1, 2006
    Inventors: Colin Wai Mun Leong, Richard Miller, Jagdeep Singh Bal