Abstract: An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.

Abstract: An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

Abstract: Methods and apparatus for improving the effects of display underflow using a variable horizontal blanking interval are disclosed. One embodiment of the present invention is a method of display that includes detecting a data ready signal that indicates availability of display data for transmission from a display pipeline, and generating a line-transmit signal based upon a clock signal and the data ready signal. The line-transmit signal is provided to the display pipeline. The line-transmit signal is substantially coincident with the clock signal if the data ready signal is set, and may be delayed if the data ready signal is not asserted. The display pipeline transmits the display data upon receiving the line-transmit signal.

Abstract: Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

Abstract: A method and device for operating a data link having multiple data lanes is provided. The method includes supplying first data (such as video data that follows the DisplayPort protocol) on one or more data lanes of a data interface between a video source device and a video sink device. In addition to being video stream data (such as the above mentioned DisplayPort video data) the first data can also be audio stream data (such as DisplayPort audio data), source-sink interface configuration data (such as DisplayPort AUX data) and sink related interrupt data (such as DisplayPort Hot Plug Detect “HPD” data). The method also includes receiving second data on one or more unidirectional data lanes of the data interface. The second data being data other than video stream data, source-sink interface configuration data and sink related interrupt data.

Abstract: A method and device for operating a data link having multiple data lanes is provided. The method includes supplying first data (such as video data that follows the DisplayPort protocol) on one or more data lanes of a data interface between a video source device and a video sink device. In addition to being video stream data (such as the above mentioned DisplayPort video data) the first data can also be audio stream data (such as DisplayPort audio data), source-sink interface configuration data (such as DisplayPort AUX data) and sink related interrupt data (such as DisplayPort Hot Plug Detect “HPD” data). The method also includes receiving second data on one or more unidirectional data lanes of the data interface. The second data being data other than video stream data, source-sink interface configuration data and sink related interrupt data.

Abstract: Provided herein is a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal.

Abstract: In an embodiment, a graphics processing device is provided. The graphics processing device includes a global clock generator configured to generate a global clock signal and a plurality of graphics pipelines each configured to transmit image frames to a respective display device. Each of the graphics pipelines comprises a timing generator. Each of the timing generators is configured to generate a respective virtual clock signal based on the global clock signal and wherein each virtual clock signal is used to advance logic of a respective one of the display devices.

Abstract: Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

Abstract: Systems, methods, and computer readable storage mediums for arbitrating the sending of display data to a plurality of displays that are coupled to a controller are disclosed. A method for arbitrating display data requests for a plurality of displays coupled to a controller includes, providing display data to a display in the plurality of displays based upon a relative priority of the display amongst the plurality of displays.

Abstract: Provided herein is a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal.

Abstract: A method and apparatus provides for providing an indication of a static frame. In one example, the method and apparatus notifies the arrival of a static frame by changing a vertical blanking interval for the static frame. For example, the method and apparatus may determine that a display frame is a static frame if no graphic processing activity and/or lack of update to the frame buffer have been detected for a period of time. In response to a display frame being a static frame, the method and apparatus may change the vertical blanking interval that is immediately before the static frame by increasing the number of blanking scan lines in the vertical blanking interval. The changed vertical blanking interval may be transmitted with the static frame as an indicator of the arrival of a static frame, so that the apparatus may enter a self-refresh mode to repeatedly display the static frame.

Abstract: A method and apparatus provides for providing a static frame. In one example, the method and apparatus divides a frame into regions and sends the divided regions of the frame from a display data transmitter, e.g., a processor such as a graphic processing unit (GPU), to a display data receiver, e.g., a timing controller (TCON). In a self-refresh mode when the frame is static, the method and apparatus detects alteration of one or more regions in the static frame. The alteration may be due to data errors in one or more regions of the static frame captured by the display data receiver and/or due to updated content (e.g., movement of a cursor) in one or more regions of the static frame in the display data transmitter. The method and apparatus then, in one example, only resends those altered regions from the display data transmitter to the display data receiver to redress the alteration.

Abstract: Systems and methods for synchronizing a source and sink device are disclosed. A sink device can efficiently determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method for transmitting a source data stream from a source device to a sink device includes, forming a logical channel from a source device to a sink device, where the logical channel is configured to carry the source data stream, and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel.

Abstract: Methods and apparatus for improving the effects of display underflow using a variable horizontal blanking interval are disclosed. One embodiment of the present invention is a method of display that includes detecting a data ready signal that indicates availability of display data for transmission from a display pipeline, and generating a line-transmit signal based upon a clock signal and the data ready signal. The line-transmit signal is provided to the display pipeline. The line-transmit signal is substantially coincident with the clock signal if the data ready signal is set, and may be delayed if the data ready signal is not asserted. The display pipeline transmits the display data upon receiving the line-transmit signal.

Abstract: An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

Abstract: An apparatus includes a clock circuit and a virtual pixel clock circuit. The clock circuit provides a common clock signal. The virtual pixel clock circuit provides a plurality of pixel clock signals in response to the common clock signal. One of the virtual pixel clock signals is at a different clock speed than another of the plurality of virtual pixel clock signals.

Abstract: A method and apparatus for frame synchronization in a display circuit is achieved by first measuring a difference between a first frame period and a second frame period. When the difference exceeds a threshold, the first frame period is adjusted by replacing the clock corresponding to the first frame period with one of a slow frame rate and a fast frame rate. The slow and fast frame rates closely approximate an ideal frame rate that would synchronize the two frame periods. By switching between the slow and fast frame rates, the average frame rate approaches the ideal frame rate over time, and the two frame periods are effectively synchronized.

Abstract: A method and apparatus for processing video signals to a plurality of video outputs may be done within a video system that includes a video decoder, a digital-to-analog module, and an output control module. In such a video system, the video decoder includes an analog-to-digital conversion module for converting an input video signal(s) into a digital video signal(s). The video decoder further includes a comb filter that is operably coupled to receive the digital video signal and to produce therefrom a Y component digital signal and a C component digital signal. The output control module is operably coupled to receive the Y and C component digital signals and also to receive an output command. If the output command dictates, the output control module provides the Y and C component digital signals to the digital-to-analog module. In response, the digital-to-analog module produces a composite video output and an S video output.