Patents by Inventor Conan Chiang
Conan Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230223292Abstract: In some examples, a flat Bottom Shadow Ring (fBSR) is provided for processing a substrate in a processing chamber. An example fBSR comprises an overhang for covering an edge of the substrate in the processing chamber. The overhang includes a fiat zone that extends radially outward over the outer edge of the substrate.Type: ApplicationFiled: June 10, 2021Publication date: July 13, 2023Inventors: Lai Wei, Ji Soo Kim, Alan Jeffrey Miller, William Thie, Frank Yun Lin, Jun Hee Hee Han, Jie Liu, Conan Chiang, Michael John Martin
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Patent number: 9384979Abstract: A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film.Type: GrantFiled: September 28, 2012Date of Patent: July 5, 2016Assignee: Lam Research CorporationInventors: Dae-Han Choi, Jisoo Kim, Eric Hudson, Sangheon Lee, Conan Chiang, S. M. Reza Sadjadi
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Patent number: 8592318Abstract: A method for etching an etch layer disposed over a substrate and below an antireflective coating (ARC) layer and a patterned organic mask with mask features is provided. The substrate is placed in a process chamber. The ARC layer is opened. An oxide spacer deposition layer is formed. The oxide spacer deposition layer on the organic mask is partially removed, where at least the top portion of the oxide spacer deposition layer is removed. The organic mask and the ARC layer are removed by etching. The etch layer is etched through the sidewalls of the oxide spacer deposition layer. The substrate is removed from the process chamber.Type: GrantFiled: November 7, 2008Date of Patent: November 26, 2013Assignee: Lam Research CorporationInventors: Jisoo Kim, Conan Chiang, Jun Shinagawa, S. M. Reza Sadjadi
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Patent number: 8357434Abstract: A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film.Type: GrantFiled: December 13, 2005Date of Patent: January 22, 2013Assignee: Lam Research CorporationInventors: Dae-han Choi, Jisoo Kim, Eric Hudson, Sangheon Lee, Conan Chiang, S. M. Reza Sadjadi
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Publication number: 20120052683Abstract: A method for etching an etch layer disposed over a substrate and below an antireflective coating (ARC) layer and a patterned organic mask with mask features is provided. The substrate is placed in a process chamber. The ARC layer is opened. An oxide spacer deposition layer is formed. The oxide spacer deposition layer on the organic mask is partially removed, where at least the top portion of the oxide spacer deposition layer is removed. The organic mask and the ARC layer are removed by etching. The etch layer is etched through the sidewalls of the oxide spacer deposition layer. The substrate is removed from the process chamber.Type: ApplicationFiled: November 7, 2008Publication date: March 1, 2012Applicant: LAM RESEARCH CORPORATIONInventors: Jisoo Kim, Conan Chiang, Jun Shinagawa, S.M. Reza Sadjadi
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Patent number: 7690966Abstract: A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.Type: GrantFiled: July 21, 2008Date of Patent: April 6, 2010Assignee: Lam Research CorporationInventors: Ramesh Gopalan, Sridharan Srivatsan, Katgenhalli Y. Ramanujam, Tom Ni, Conan Chiang
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Patent number: 7476610Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.Type: GrantFiled: November 10, 2006Date of Patent: January 13, 2009Assignee: Lam Research CorporationInventors: Ji Soo Kim, Conan Chiang, Daehan Choi, S. M. Reza Sadjadi, Michael Goss
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Patent number: 7413988Abstract: A method for planarizing a semiconductor substrate is provided. The method initiates with tracking a signal corresponding to a thickness of a conductive film disposed on the semiconductor substrate. Then, a second derivative is calculated from data representing the tracked signal. Next, the onset of planarization is identified based upon a change in the second derivative. A CMP system configured to identify a transition between stages of the CMP operation is also provided.Type: GrantFiled: June 27, 2003Date of Patent: August 19, 2008Assignee: Lam Research CorporationInventors: Ramesh Gopalan, Sridharan Srivatsan, Katgenhalli Y. Ramanujam, Tom Ni, Conan Chiang
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Publication number: 20080111166Abstract: A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.Type: ApplicationFiled: November 10, 2006Publication date: May 15, 2008Inventors: Ji Soo Kim, Conan Chiang, Daehan Choi, S. M. Reza Sadjadi, Michael Goss
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Publication number: 20070181530Abstract: A method of forming features in an etch layer disposed below a mask with features is provided. The mask is conditioned. The conditioning, comprising providing a conditioning gas consisting essentially of at least one noble gas, forming a plasma from the conditioning gas, and exposing the mask to the plasma from the conditioning gas. The features of the mask are shrunk. Features are etched into the etch layer through the shrunk features of the mask.Type: ApplicationFiled: February 8, 2006Publication date: August 9, 2007Inventors: Zhi-Song Huang, S.M. Sadjadi, Lumin Li, Conan Chiang
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Patent number: 6617257Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.Type: GrantFiled: March 30, 2001Date of Patent: September 9, 2003Assignee: Lam Research CorporationInventors: Tuqiang Ni, Weinan Jiang, Conan Chiang, Frank Y. Lin, Chris Lee, Dai N. Lee
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Publication number: 20020182881Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defmed by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.Type: ApplicationFiled: March 30, 2001Publication date: December 5, 2002Inventors: Tuqiang Ni, Weinan Jiang, Conan Chiang, Frank Y. Lin, Chris Lee, Dai N. Lee