Patents by Inventor Connor Burgess

Connor Burgess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990386
    Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 21, 2024
    Assignee: Google LLC
    Inventors: Madhusudan K. Iyengar, Christopher Malone, Woon-Seong Kwon, Emad Samadiani, Melanie Beauchemin, Padam Jain, Teckgyu Kang, Yuan Li, Connor Burgess, Norman Paul Jouppi, Nicholas Stevens-Yu, Yingying Wang
  • Publication number: 20240070428
    Abstract: Aspects of the disclosure provide tracking tags. As an example, a tracking tag may include beacon transmission circuitry including one or more batteries, a frame configured to hold the one or more batteries in place, an adhesive arranged to secure the tracking tag to an object, and an activation mechanism configured to activate the tracking tag and cause the beacon transmission circuitry to transmit beacon signals in order to enable tracking of the object.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 29, 2024
    Inventors: Ricky Yik Hei Ngan, Phillip Yee, Connor Burgess, Dean Kawaguchi, Kin Seto, Russell Shikami
  • Publication number: 20230260931
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Patent number: 11721641
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 8, 2023
    Assignee: Google LLC
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Patent number: 11664329
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 30, 2023
    Assignee: Google LLC
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Publication number: 20230037380
    Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.
    Type: Application
    Filed: October 21, 2022
    Publication date: February 9, 2023
    Inventors: Jorge Padilla, Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Yuan Li, Feini Zhang
  • Patent number: 11488890
    Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: November 1, 2022
    Assignee: Google LLC
    Inventors: Jorge Padilla, Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Yuan Li, Feini Zhang
  • Publication number: 20210378106
    Abstract: A method of manufacturing a chip assembly comprises joining an in-process unit to a printed circuit board; reflowing a bonding material disposed between and electrically connecting the in-process unit with the printed circuit board, the bonding material having a first reflow temperature; and then joining a heat distribution device to the plurality of semiconductor chips using a thermal interface material (“TIM”) having a second reflow temperature that is lower than the first reflow temperature. The in-process unit further comprises a substrate having an active surface, a passive surface, and contacts exposed at the active surface; an interposer electrically connected to the substrate; a plurality of semiconductor chips overlying the substrate and electrically connected to the substrate through the interposer, and a stiffener overlying the substrate and having an aperture extending therethrough, the plurality of semiconductor chips being positioned within the aperture.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 2, 2021
    Inventors: Madhusudan K. Iyengar, Christopher Malone, Woon-Seong Kwon, Emad Samadiani, Melanie Beauchemin, Padam Jain, Teckgyu Kang, Yuan Li, Connor Burgess, Norman Paul Jouppi, Nicholas Stevens-Yu, Yingying Wang
  • Publication number: 20210366841
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Publication number: 20210366806
    Abstract: Systems and methods for using spring force based compliance to minimize the bypass liquid flow gaps between the tops of chip microfins and bottom side of manifold ports are disclosed herein. A fluid delivery and exhaust manifold structure provides direct liquid cooling of a module. The manifold sits on top of a chip with flow channels. Inlet and outlet channels of the manifold in contact with flow channels of the chip creates an intricate crossflow path for the coolant resulting in improved heat transfer between the chip and the working fluid. The module is also designed with pressure reduction features using internal leakage flow openings to account for pressure differential between fluid entering and being expelled from the module.
    Type: Application
    Filed: May 20, 2020
    Publication date: November 25, 2021
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Emad Samadiani, Padam Jain, Jorge Padilla, Feini Zhang, Yuan Li
  • Publication number: 20210366807
    Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Jorge Padilla, Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Yuan Li, Feini Zhang