Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the events.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events.

Abstract: Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.

Abstract: In one aspect, the invention provides parallel processing apparatus comprising an array of data processors 4. arranged to operate synchronously, and a plurality of data buses. Each data processor 4 has first and second I/O means 16H, 16V for transfer of data between the processor 4 and respective data buses H,V a plurality of processors 4 being connected to each of the data buses H,V and each processor 4 being connected, via said I/O means 16H, 16V, to a different pair of data buses H,V. Each processor 4 includes selectively operable routing means 32H, 32V for interconnecting the first and second I/O means 16H, 16V to transfer data between the buses H,V connected thereto.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A, B of the system in dependence upon the event to be indicated, the pairs of memory locations A, B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A, B; processing the data read from each pair of memory locations A, B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor.

Abstract: Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.