Abstract: An apparatus, system, and method are disclosed for asymmetric maximum likelihood detection. An initialization module initializes a plurality of branch metrics and a plurality of path memories. A coefficient module calculates a plurality of coefficients. A computation module calculates a first and second specified likelihood function. A selection module calculates a third specified branch metric as the maximum of the first and second specified likelihood functions. A path metrics module calculates a third specified path memory from a first and second specified path memory. A results module identifies a data output value from one or more path memories.

Abstract: A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These "side-samples" contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error.

Abstract: A system for encoding and decoding binary data in a data transmission system, such as a magnetic or optical data storage channel. The encoding process is implemented as a two-step RLL coding procedure wherein the original user bit data are first encoded as an asymmetric RLL code signal at a reduced clock rate and then translated to a second even-spaced RLL code signal suitable for recording to a data storage medium at a full-speed clock rate. The system also provides for recovering suitable even-spaced RLL codes recorded at a full-speed clock rate, translating the recovered even-spaced RLL code signal to an asymmetric RLL code signal at a reduced clock rate, and then decoding the asymmetric RLL code signal to recover the original user bit data. A preferred embodiment uses a rate 2/5 (2, 16, 2) even-spaced RLL code at a full-speed clock rate and a rate 4/5 (0,7; 1,8) asymmetric RLL code at a half-speed clock rate.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A method is disclosed for recovery from synchronization errors caused by deletions and/or insertions of symbols in the presence of errors that alter the symbols in any code constrained binary record. The method initially divides the sequence of data into equal size blocks before appending a binary sync sequence at the end of each block not encountered in the block. Then, the blocks are resynchronized by first determining the size of any symbol insertions and/or deletions that have occurred. Then, scanning for the sync sequence starting at the presumed end of the data field of the current block so as to determine the offset of the sync sequence with respect to that specific location. After this location of the insertions and/or deletions has been determined, a corresponding number of symbols can be added or deleted from the middle of the block according to the offset determined by the present method.

Abstract: A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.

Abstract: A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.

Abstract: A variable sampling-rate digital channel phase detector for reading synchronous data recordings from magnetic or optical media. All-digital implementation allows multiplexing of several parallel channels on a single monolithic chip for tape storage systems or other magnetic or optical data storage systems. The ASDD channel signal processing is entirely digital and includes A/D converter, digital filter and equalizer, digital differentiator and zero-crossing detector, peak amplitude estimator, zero-crossing qualifier and zero-crossing position (phase) estimator. The ASDD input is an analog waveform and the output includes two flags for qualified negative and positive waveform threshold-crossings and a digital signal encoding a waveform threshold-crossing position within the current sampling clock interval. The ASDD operates over a wide continuous range of channel data rates and provides accurate phase detection at relatively low sampling rates.

Abstract: A pulse signal conditioner filters and equalizes signal pulses representing digital data whether or not obtained from a magnetic recording device. Modified low pass filters filter the pulse signals and also derive and feed forward the second time derivative of the filtered pulse signals. The filtered pulse and the second time derivative thereof are combined to slim the pulse. Further slimming is provided by delay line equalizers having three paths. A first path for attenuating the pulse signals, a second path for delaying the pulse signals for a first delay, and a third path for delaying the pulse signals for a second delay and attenuation. Pulse signals from the three paths are combined to further slim the pulse.

Abstract: An equalizer circuit is shown which conditions a read back signal from a data storage device by performing amplitude correction (pulse slimming) and phase correction. The circuit provides a simplified single stage that effects both amplitude and phase correction and does so using components that can be selected or adjusted independently of one another. Further, the principal embodiment shows a single ended circuit that provides the function with a minimum number of components to conserve space on the circuit card as well as reducing cost.

Abstract: To increase storage capacity of a disk storage device, the recording surface of the device is partitioned into a plurality of concentric recording bands, data to be recorded on respective bands are encoded using different run-length-limited codes with the code rate of each band being higher than the adjacent inner band.

Abstract: A switching network is comprised of a plurality of identical chips and a network (control) processor. Each of the chips is a novel intelligent switch and includes both a cross point array as well as apparatus to control the cross point array in response to a set of multi bit commands or to formulate a response to a query concerning status of the switching array. The number of command lines connecting network (control) processor to each of the array chips may be as few as two. The cross point array includes a cross point device (switch) for each inlet-outlet combination. The total number of cross points in the network is lower than that dictated by a CLOS network.

Abstract: A method for rearranging a three stage (primary, intermediate, tertiary) switching network to permit data or digitized voice signals to be transmitted from any given primary outlet to any given tertiary inlet. The intermediate stage has fewer inlets than the number of primary stage outlets and fewer outlets than the number of tertiary stage inlets, making the network a conditionally blocking one. Two call rearranging buses are provided to assure that each signal path being rearranged is maintained to prevent data transmission dropout. Primary to intermediate and intermediate to tertiary paths are rearranged one at a time using the call rearranging buses to move free primary and tertiary links to a single intermediate matrix.