Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7c) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: The performance of high-voltage devices is often influenced by charge-creep effects in the package. In order to avoid the resultant degradation, a bleeder may be used between the device and the package. However, it has been found in practice that the use of a high-resistive bleeder may lead to a certain instability of the device during operation. According to the invention, the bleeder (8) is provided with a plurality of conductive regions (12, 13) which are distributed in such a way that, when a high voltage is applied across the bleeder, a non-linear potential profile across the bleeder is obtained, which harmonizes with the ideal potential profile without the bleeder, instead of a linear profile which would have been obtained in the absence of said conductive regions due to charge-loading effects, and which would result in the above-mentioned instability effects.

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: In an integrated circuit (IC) for providing an enabling signal (EN) to a converter, the integrated circuit (IC) includes a monitoring circuit (FET1, R2, D1, Io, M, S1) for providing a control signal (CS) in response to a level of a line voltage (Vline) on a first connection terminal (8) of the integrated circuit (IC), and a start-up circuit (FET2, Istrt_up, Vcc_strt-Lev, COMP, S2) for providing the enabling signal (EN) to the converter in response to the control signal (CS) and a generated voltage level (Vcc), the generated voltage level (Vcc) being generated in response to the level of the line voltage (Vline) on the first connection terminal (8). The monitoring circuit and the start-up circuit sense the level of the line voltage (Vline) only via the first connection terminal (8).

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.

Abstract: In an integrated circuit (IC) for providing an enabling signal (EN) to a converter, the integrated circuit (IC) comprising:

Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7d) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.