Abstract: A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range.

Abstract: A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range.

Abstract: In a method and a circuit arrangement for preventing interference pulses in the intermediate frequency signal in an AM receiver comprising a mixer, in which a high frequency signal fed to the mixer is blanked out when interference occurs, it is provided that, while the high frequency signal is blanked out, a filter provided for the intermediate frequency signal is undamped.

Abstract: A circuit (100) for detecting the duty cycle of clock signals comprises an oscillator (2) whose signal can be changed into a square-wave voltage in a gate (3). In order to obtain a simple construction of the circuit (100) with improved quality of the output signals a low-pass filter (3) is provided whose output signal is situated between “low” and “high”.

Abstract: A circuit arrangement for a resistor of high linearity that can be produced in integrated technology and be controlled by the current (Io1, Io2), which circuit arrangement is constructed from two pairs of transistors comprising transistors (T1 . . . T4) of the same junction type connected as diodes. Each pair of transistors (T1, T2 and T3, T4) has a common point of connection (D, E) that connects together the anodes of one pair of diodes and the cathodes of the other pair. The point of connection (D) of the first pair of transistors (T1, T2) is situated on their collector lines and thus connects the anodes and forms the infeed point for a first control current source (Io1). The point of connection (E) of the second pair of transistors connects the cathodes and is thus situated on their emitter lines and forms the infeed point for a second control current source (Io2).

Abstract: The invention relates to a circuit arrangement for a current-controlled resistor having an enlarged linear range, using an arrangement of non-linear bipolar load elements wherein the resistance is generated between a first terminal (E) and a second terminal (F), having at least one control terminal (X) that is fed by a supply current source (I1), wherein the arrangement of the non-linear bipolar load elements comprises at least a third chain (C) comprising one or more of the load elements (DCl . . . DCi), the load elements being connected in series where there is more than one of them, and comprises a first chain (A) and a second chain (B) each comprising one or more load elements (DAl . . . DAj and DBl . . .

Abstract: In a circuit arrangement for demodulating signals, particularly frequency-modulated signals, in which a limiter, to whose input the signals to be modulated can be applied, is followed by a demodulator from whose output the demodulated signals can be derived, the outputs of the demodulator and the limiter are connected to a respective input of a mixer whose output is connected to the input of the limiter via a low-pass filter.

Abstract: A circuit arrangement for a resistor of high linearity that can be produced in integrated technology and be controlled by the current (Io1, Io2), which circuit arrangement is constructed from two pairs of transistors comprising transistors (T1 . . . T4) of the same junction type connected as diodes. Each pair of transistors (T1, T2 and T3, T4) has a common point of connection (D, E) that connects together the anodes of one pair of diodes and the cathodes of the other pair. The point of connection (D) of the first pair of transistors (T1, T2) is situated on their collector lines and thus connects the anodes and forms the infeed point for a first control current source (Io1). The point of connection (E) of the second pair of transistors connects the cathodes and is thus situated on their emitter lines and forms the infeed point for a second control current source (Io2).

Abstract: The invention relates to a circuit arrangement for a current-controlled resistor having an enlarged linear range, using an arrangement of non-linear bipolar load elements wherein the resistance is generated between a first terminal (E) and a second terminal (F), having at least one control terminal (X) that is fed by a supply current source (I1), wherein the arrangement of the non-linear bipolar load elements comprises at least a third chain (C) comprising one or more of the load elements (DC1 . . . DCi), the load elements being connected in series where there is more than one of them, and comprises a first chain (A) and a second chain (B) each comprising one or more load elements (DA1 . . . DAj and DB1 . . .

Abstract: The invention relates to an arrangement for forming a reciprocal value of an input current (Iin), comprising: a power supply source (22); a current source (21) for generating a current (I0) for adjusting at least one operating point; a diode circuit with two devices operating as diodes (30, 31 and Q1, Q2), which are coupled in series; a transistor (Q3), in which a base of the transistor (Q3) is coupled between the diode circuit and the current source and in which a collector of the transistor (Q3) is coupled between the current source and the power supply source; and a further transistor (Q4), in which a base of the further transistor (Q4) is coupled to an emitter of the transistor (Q3) and an input current terminal and in which an emitter of the further transistor (Q4) is connected to the input current terminal of the diode circuit and the power supply source in such a way that an output current (Iout) flowing through the collector of the further transistor (Q4) is proportional to the reciprocal value of the

Abstract: A comparator circuit for comparing two electric voltages, the comparator circuit comprising a differential amplifier with a current mirror as a load, characterized in that two current branches comprise two differential transistor amplifiers (2, 3) with two current mirrors (4, 5) as a load, in which the bases of the differential amplifiers (2, 3) represent the comparator input, and in that both current mirrors (4, 5) are each constituted by a diode (6, 9) and an associated transistor (7, 8), in which the comparator output value is either one of the currents through the diodes (6, 9) or one of the voltages across the diodes (6, 9) or the difference between the two diode voltages (6, 9).

Abstract: In order to provide a circuit arrangement (100) for generating and amplifying a DC signal, referred to as level voltage, whose value is essentially proportional to the logarithm of the voltage amplitude of the input signal, the circuit arrangement comprising an amplifier circuit having at least two amplifier stages (10; 20; 30), it is proposed that at least a differential amplifier stage (40), in particular non-negatively fed back, is arranged parallel to the last amplifier stage (30), particularly parallel to the collector circuits of the last amplifier stage (30), the differential amplifier stage (40) precedes at least a multiplier stage (50) for multiplying the output signals of the differential amplifier stage (40), for generating two differential amplifier output signals which are to be multiplied by each other, and alternatively to the differential amplifier (40), the collector currents of the transistors (36, 38) of the rectifier circuit (35) of the last amplifier stage (30) are used, and at least a cu

Abstract: In a circuit arrangement for demodulating signals, particularly frequency-modulated signals, in which a limiter, to whose input the signals to be modulated can be applied, is followed by a demodulator from whose output the demodulated signals can be derived, the outputs of the demodulator and the limiter are connected to a respective input of a mixer whose output is connected to the input of the limiter via a low-pass filter.

Abstract: The invention relates to an arrangement for forming a reciprocal value of an input current (Iin), comprising: a power supply source (22); a current source (21) for generating a current (I0) for adjusting at least one operating point; a diode circuit with two devices operating as diodes (30, 31 and Q1, Q2), which are coupled in series; a transistor (Q3), in which a base of the transistor (Q3) is coupled between the diode circuit and the current source and in which a collector of the transistor (Q3) is coupled between the current source and the power supply source; and a further transistor (Q4), in which a base of the further transistor (Q4) is coupled to an emitter of the transistor (Q3) and an input current terminal and in which an emitter of the further transistor (Q4) is connected to the input current terminal of the diode circuit and the power supply source in such a way that an output current (Iout) flowing through the collector of the further transistor (Q4) is proportional to the reciprocal value of the

Abstract: To provide a circuit arrangement (100) and a method for generating and amplifying an amplitude-limited DC signal whose level voltage is substantially proportional to the logarithm of the voltage amplitude of an input signal, by which the level indication, i.e.

Abstract: To provide a circuit arrangement (100) and a method for generating and amplifying an amplitude-limited DC signal whose level voltage is substantially proportional to the logarithm of the voltage amplitude of an input signal, by which the level indication, i.e.