Patents by Inventor Cordell E. Prater

Cordell E. Prater has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4884240
    Abstract: A static row driver for an array of memory cells which includes a plurality of NAND gates each having a pair of row line driver input signals, an inverter coupled to an output of each of the NAND gates, a switch coupled to an output of each of the inverter circuits and a switch control coupled to each of the switches for opening an associated switch and passing the signal from a corresponding inverter output to an associated row line.
    Type: Grant
    Filed: June 19, 1986
    Date of Patent: November 28, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Stanley M. Dennison, Cordell E. Prater
  • Patent number: 4612457
    Abstract: An output buffer in an MOS integrated circuit is adapted to provide high output currents to meet high performance requirements under varying operating conditions and has voltage responsive MOS means limiting output current under certain operating conditions to assure circuit reliability while permitting restriction of circuit buss capacities within desirable limits.
    Type: Grant
    Filed: June 27, 1983
    Date of Patent: September 16, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Cordell E. Prater
  • Patent number: 4553051
    Abstract: A PMOS input buffer compatible with logic voltage levels provided by NMOS or TTL microprocessor means uses a limited number of transistors of limited size for driving a load in response to such logic and is adapted for use under widely varying operating conditions.
    Type: Grant
    Filed: July 18, 1983
    Date of Patent: November 12, 1985
    Assignee: Texas Instruments Incorporated
    Inventor: Cordell E. Prater
  • Patent number: 4365172
    Abstract: A static push-pull driver circuit employs an enhancement mode input transistor and two parallel load transistors, with an input logic voltage on the gate of the input transistor and its complement on the gates of the load transistors. One load transistor is a depletion mode and the other a "low-threshold" device; the threshold voltage of the low-threshold transistor is much less than that of the enhancement mode input transistor.
    Type: Grant
    Filed: January 11, 1980
    Date of Patent: December 21, 1982
    Assignee: Texas Instruments Incorporated
    Inventor: Cordell E. Prater