Patents by Inventor Corey Petersen
Corey Petersen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11550029Abstract: Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.Type: GrantFiled: July 16, 2020Date of Patent: January 10, 2023Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANYInventors: Vinoth Kumar, Satishchandra G. Rao, Corey Petersen, Madhusudan Rathi, Gerard E. Taylor, Kaustubh Mundhada
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Publication number: 20220018931Abstract: Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.Type: ApplicationFiled: July 16, 2020Publication date: January 20, 2022Applicant: Analog Devices International Unlimited CompanyInventors: Vinoth KUMAR, Satishchandra G. RAO, Corey PETERSEN, Madhusudan RATHI, Gerard E. TAYLOR, Kaustubh MUNDHADA
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Patent number: 10340934Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.Type: GrantFiled: December 18, 2017Date of Patent: July 2, 2019Assignee: ANALOG DEVICES, INC.Inventors: Nevena Rakuljic, Carroll C. Speir, Eric Otte, Corey Petersen, Jeffrey P. Bray
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Publication number: 20190190530Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Applicant: Analog Devices, Inc.Inventors: Nevena RAKULJIC, Carroll C. SPEIR, Eric OTTE, Corey PETERSEN, Jeffrey P. BRAY
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Patent number: 9912144Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.Type: GrantFiled: September 4, 2014Date of Patent: March 6, 2018Assignee: ANALOG DEVICES GLOBALInventors: Trevor Clifford Caldwell, Corey Petersen, David Nelson Alldred, Hajime Shibata
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Publication number: 20160072275Abstract: Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.Type: ApplicationFiled: September 4, 2014Publication date: March 10, 2016Applicant: ANALOG DEVICES TECHNOLOGYInventors: TREVOR CLIFFORD CALDWELL, COREY PETERSEN, DAVID NELSON ALLDRED, HAJIME SHIBATA
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Patent number: 9071205Abstract: An amplifier with a single-input class-AB output stage comprises an input stage providing a signal to an output stage. The output stage comprises a current-splitting stage having a bias current and providing at least two intermediate output currents, and a drive stage receiving the two intermediate output currents and driving an output signal having a positive side and a negative side.Type: GrantFiled: June 7, 2013Date of Patent: June 30, 2015Assignee: Analog Devices, Inc.Inventors: Daniel Rey-Losada, Corey Petersen
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Publication number: 20140361833Abstract: An amplifier with a single-input class-AB output stage comprises an input stage providing a signal to an output stage. The output stage comprises a current-splitting stage having a bias current and providing at least two intermediate output currents, and a drive stage receiving the two intermediate output currents and driving an output signal having a positive side and a negative side.Type: ApplicationFiled: June 7, 2013Publication date: December 11, 2014Inventors: Daniel Rey-Losada, Corey Petersen
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Patent number: 7424066Abstract: Receiver embodiments are disclosed that can process a wide range of transmission bandwidths over a wide range of transmission frequencies and provide reduced converter sampling rates, filter bandwidths, and filter tuning ranges and enhanced signal-to-noise performance. They convert transmission signals with quadrature local oscillator signals whose frequencies are commanded to be a selected transmission frequency when a selected transmission bandwidth is above a predetermined bandwidth threshold and are commanded to be offset from the selected transmission frequency by an intermediate frequency that is at least one half of the selected transmission bandwidth when the selected transmission bandwidth is below the bandwidth threshold.Type: GrantFiled: January 21, 2005Date of Patent: September 9, 2008Assignee: Analog Devices, Inc.Inventors: Antonio J. Montalvo, Corey Petersen
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Publication number: 20060165196Abstract: Receiver embodiments are disclosed that can process a wide range of transmission bandwidths over a wide range of transmission frequencies and provide reduced converter sampling rates, filter bandwidths, and filter tuning ranges and enhanced signal-to-noise performance.Type: ApplicationFiled: January 21, 2005Publication date: July 27, 2006Inventors: Antonio Montalvo, Corey Petersen
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Patent number: 4490629Abstract: A CMOS push-pull output buffer (171) is constructed utilizing a plurality of N channel transistors (74, 75, 76) and a plurality of P channel transistors (71, 72, 73) connected in series. The voltages applied to the gates of the N channel transistors and P channel transistors are selected to divide the high voltage (+V) substantially equally across the P channel transistors, when the P channel transistors are turned off, and substantially evenly divide the high voltage across the N channel transistors, when the N channel transistors are turned off.In another embodiment of this invention, selected ones of the N channel and P channel transistors are formed in order to have a high drain to bulk breakdown voltage.In another embodiment of this invention, a plurality of N channel and a plurality of P channel transistors are connected in series and driven by a single ended control voltage (C.sub.Type: GrantFiled: May 10, 1982Date of Patent: December 25, 1984Assignee: American Microsystems, Inc.Inventors: Allen R. Barlow, Corey Petersen
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Patent number: D914838Type: GrantFiled: August 28, 2018Date of Patent: March 30, 2021Assignee: AS AMERICA INC.Inventors: David Grover, Corey Petersen, Ki Bok Song
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Patent number: D950008Type: GrantFiled: February 24, 2021Date of Patent: April 26, 2022Assignee: AS America, Inc.Inventors: David Grover, Corey Petersen, Ki Bok Song