Abstract: A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

Abstract: An attenuation device for a CAN transceiver comprises two device output nodes configured to electrically couple the attenuation device via the device output nodes between two transceiver terminals of the CAN transceiver. The attenuation device is configured to change from a first device state to a second device state when a common mode voltage is applied to the device output nodes that is either greater than a first reference voltage or less than a second reference voltage that is less than the first reference voltage. The attenuation device causes a first electrical output resistance at each device output node during the first device state and causes a second electrical output resistance at each device output node during the second device state in which the second output resistance is less than the first output resistance.

Abstract: The disclosure relates to a Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal.

Abstract: An apparatus, method and integrated circuit for broad-range current measurement using duty cycling are disclosed. Embodiments of an apparatus for sensing current through a transistor device may include an interface configured to receive a current from the transistor device for sensing. Additionally, embodiments may include a sensor component coupled to the interface and configured to receive the current from the transistor device and to generate a responsive sensor voltage. Embodiments may also include a sense control circuit configured to control a duty cycle of the sensor component.

Abstract: An apparatus, method and integrated circuit for broad-range current measurement using variable resistance are disclosed. Embodiments of an apparatus for sensing current through a transistor device may include an interface configured to receive a current from the transistor device for sensing. In an embodiment, the apparatus may also include a sensor component coupled to the interface and configured to receive the current from the transistor device and to generate a responsive sensor voltage, the sensor component comprising an adjustable resistance component, a resistance value of the adjustable resistance component being selectable in response to a level of the current received at the interface.

Abstract: An apparatus, method and integrated circuit for broad-range current measurement using duty cycling are disclosed. Embodiments of an apparatus for sensing current through a transistor device may include an interface configured to receive a current from the transistor device for sensing. Additionally, embodiments may include a sensor component coupled to the interface and configured to receive the current from the transistor device and to generate a responsive sensor voltage. Embodiments may also include a sense control circuit configured to control a duty cycle of the sensor component.

Abstract: An apparatus, method and integrated circuit for broad-range current measurement using variable resistance are disclosed. Embodiments of an apparatus for sensing current through a transistor device may include an interface configured to receive a current from the transistor device for sensing. In an embodiment, the apparatus may also include a sensor component coupled to the interface and configured to receive the current from the transistor device and to generate a responsive sensor voltage, the sensor component comprising an adjustable resistance component, a resistance value of the adjustable resistance component being selectable in response to a level of the current received at the interface.

Abstract: An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.

Abstract: An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.

Abstract: An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.

Abstract: An interference-tolerant transmitter is provided. In accordance with various example embodiments, a transmitter circuit includes a control circuit configured to maintain the sum of current as applied to a load from respective high-side and low-side current sources at a target level (e.g., range). In some applications, clamp circuits are used to clamp current to high and low sides of the load respectively in response to changes at the low-side and high-side of the load.

Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device,—and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device.

Abstract: The invention relates to a receiver for a differential bus with a switch control logic (151), with two branches with resistive elements (7, 61 . . . 70, 8 and 5, 11 . . . 20, 6) and with switches (3, 80) for switching the resistive elements, in which the switch control logic sets the switches—in a first routine for determining the absolute level of signals on the bus by applying a common mode voltage to the bus, by comparing the voltage on a first resistive branch with a reference voltage, by selecting the correct switch settings, and by writing these settings to an internal storage device, —and in a second routine for minimizing the mismatch between the two resistive branches by applying a common mode voltage to the bus, by comparing the voltage of the second resistive branch with that of the already trimmed first resistive branch, by selecting the correct switch settings for the second branch, and by writing these settings to an internal storage device.

Abstract: A bus communication system contains a pair of communication conductors and a driver. The driver contains a plurality of pairs of controlled current source circuit, each pair comprising current source circuits of a first and second, mutually opposite polarity, and a control circuit for matching currents drawn by the current sources in each pair. The current source circuit of the first polarity have outputs coupled to a first one of the communication conductors, the current source circuits of the second polarity have outputs coupled to a second one of the communication conductors. A delay line is provided, with taps coupled to control inputs of the current sources of the first and second polarity, so that the pairs are switched on successively with mutual delays between successive pairs, as determined by the delay line.