Abstract: The invention relates a method for testing a batch of electrical components like Integrated Circuits, the method involving applying a first test (6) on each electrical component from the batch; and applying a second test (12) on electrical components that have failed the first test (6). Advantageously, the second test (12) is applied directly after the first test (6). Preferably, the first test (6) includes a functional test, and the second test (12) includes a Contact-and-Short-Circuit test.

Abstract: The present invention relates to production testing of semiconductor devices, more specifically to production testing of such devices at wafer level. A method according to the present invention comprises the steps of generating (20) quality test-data at a limited number of semiconductor devices on the wafer, deciding (24) based on the generated quality test-data whether other semiconductor devices on the wafer are to be tested, and based on the result of the deciding step, testing (28) or not testing (26) the other semiconductor devices on the wafer. A corresponding wafer prober is also described.

Abstract: A test machine (10) is provided with a integrating circuit (102) so that when a integrated circuit (12) is inserted in the test machine an external feedback loop between an input (120a) and an output (124a) of a comparator (122) in the integrated circuit under test is established. Thus an input voltage of the comparator (122) oscillates around a threshold level of the comparator (122). A test result is determined dependent on an average value of an oscillating voltage in the feedback loop. In an embodiment the feedback loop is realized with a digital test tester (100, 104, 106) with an added analog integrating circuit added to its output (14).

Abstract: An electronic circuit device has contact terminal outside its package. The contact terminals are connected via the main current channels of two transistors connected in parallel between the contact terminals, so as to provide a switchable short circuit between the terminals. The device is tested by connecting two sense contacts of a resistance measuring device to the terminals and measuring the resistance between the sense contacts a first, second and third state respectively, the first and second transistor being switched on and off respectively in the first state and vice versa in the second state, both transistors being switched on in the third state. The resistance in the three states is modeled as a model resistance composed of a series resistance component in series with a first resistance component, a second resistance component and a parallel arrangement of said first and second resistance component respectively.

Abstract: The invention relates a method for testing a batch of electrical components like Integrated Circuits, the method comprising: applying a first test (6) on each electrical component from the batch; and applying a second test (12) on electrical components that have failed the first test (6). Advantageously, the second test (12) is applied directly after the first test (6). Preferably, the first test (6) comprises a functional test, and the second test (12) comprises a Contact-and-Short-Circuit test.

Abstract: An electronic circuit device has contact terminal outside its package. The contact terminals are connected via the main current channels of two transistors connected in parallel between the contact terminals, so as to provide a switchable short circuit between the terminals. The device is tested by connecting two sense contacts of a resistance measuring device to the terminals and measuring the resistance between the sense contacts a first, second and third state respectively, the first and second transistor being switched on and off respectively in the first state and vice versa in the second state, both transistors being switched on in the third state. The resistance in the three states is modeled as a model resistance composed of a series resistance component in series with a first resistance component, a second resistance component and a parallel arrangement of said first and second resistance component respectively.