Abstract: In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

Abstract: In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

Abstract: In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

Abstract: A method is presented including assigning a first register class to at least one symbolic register in at least one instruction, determining and assigning a second register class to the at least one register, reducing register class fixups and renaming the at least one symbolic register. Also presented is a system including a processor having at least one register and a compiler executing in the processor that inputs a source program having many operation blocks. The compiler assigns a first register class in at least one instruction to at least one symbolic register, determines and assigns a second register class to the at least one symbolic register, reduces register class fixups, and renames the at least one symbolic register.

Abstract: A program may be partitioned into at least two stages, where at least one of the stages comprises more than one parallel thread. Data required by each of the stages, which data is defined in a previous stage may be identified. Transmission of the required data between consecutive stages may then be provided for.

Abstract: The invention provides a method and apparatus for optimizing code. Embodiments of the present invention comprise, for each expression in an intermediate program representation, transparently forwarding definitions of variables in said expression as said expression is being parsed by a term rewriter, the intermediate program representation being left unchanged; determining whether a term rewriting rule exists in the term rewriter for said expression; and rewriting said expression in the intermediate program representation according to said rule.

Abstract: The invention provides a method and apparatus for doing program analysis. According to embodiments of the invention program analysis comprises assigning an alias to each equivalence class of possibly overlapping memory accesses as defined by an alias analysis of an intermediate language program; and defining a definition-use relationship between statements in each equivalence class wherein definition statements which belong to the equivalence class reference the alias associated with that class, and wherein use statements which belong to the equivalence class reference the alias associated with for that class. The invention also provides a program analysis algorithm which utilizes a dependence flow graph having the property that the edge cardinality is independent of the definition-use of structure the program being analyzed.

Abstract: A method and system for type demotion of expressions and variables by bitwise propagation is disclosed. In one embodiment, a method, comprises determining when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision, wherein the operation is contained in code associated with a language implementation system; and replacing the operation on the larger data type by the operation on the smaller data type.

Abstract: A program may be partitioned into at least two stages, where at least one of the stages comprises more than one parallel thread. Data required by each of the stages, which data is defined in a previous stage may be identified. Transmission of the required data between consecutive stages may then be provided for.

Abstract: A method is presented including assigning a first register class to at least one symbolic register in at least one instruction, determining and assigning a second register class to the at least one register, reducing register class fixups and renaming the at least one symbolic register. Also presented is a system including a processor having at least one register and a compiler executing in the processor that inputs a source program having many operation blocks. The compiler assigns a first register class in at least one instruction to at least one symbolic register, determines and assigns a second register class to the at least one symbolic register, reduces register class fixups, and renames the at least one symbolic register.

Abstract: A method of scheduling a sequence of instructions is described. A target program is read, a pipeline control hazard is identified within the sequence of instructions, and a selected sequence of instructions is re-ordered. Two steps for re-ordering are applied to the selected sequence of instructions. First, a backward scheduling method is performed, and second, a forward scheduling method is performed.

Abstract: In some embodiments, a method and apparatus for an automatic thread-partition compiler are described. In one embodiment, the method includes the transformation of a sequential application program into a plurality of application program threads. Once partitioned, the plurality of application program threads are concurrently executed as respective threads of a multi-threaded architecture. Hence, a performance improvement of the parallel multi-threaded architecture is achieved by hiding memory access latency through or by overlapping memory access with computations or with other memory accesses. Other embodiments are described and claimed.

Abstract: In some embodiments, a method and apparatus for automatically parallelizing a sequential network application through pipeline transformation are described. In one embodiment, the method includes the configuration of a network processor into a D-stage processor pipeline. Once configured, a sequential network application program is transformed into D-pipeline stages. Once transformed, the D-pipeline stages are executed in parallel within the D-stage processor pipeline. In one embodiment, transformation of a sequential application program is performed by modeling the sequential network program as a flow network model and selecting from the flow network model into a plurality of preliminary pipeline stages. Other embodiments are described and claimed.

Abstract: A method and system for bidirectional bitwise constant propogation by abstract interpretation is disclosed. In one embodiment, the method performs optimizing an implementation of a programming language, comprising; analyzing one or more values computed by a program written in the programming language, wherein analyzing one or more values comprises; representing each bit within a value of the one or more values as an abstract element of a lattice having a set of abstract elements including 0A, 1A, ?A and TA, wherein the lattice is an abstraction of a concrete domain containing 0, 1, and ?; analyzing one or more output bits that are produced by an operation in terms of one or more input bits that are input to the operation; and analyzing the input bits that are input to the operation in terms of the output bits that are produced by the operation.

Abstract: A method and system for bidirectional bitwise constant propagation by abstract interpretation is disclosed. In one embodiment, the method performs optimizing an implementation of a programming language, comprising; analyzing one or more values computed by a program written in the programming language, wherein analyzing one or more values comprises; representing each bit within a value of the one or more values as an abstract element of a lattice having a set of abstract elements including 0A, 1A, ⊥A and TA, wherein the lattice is an abstraction of a concrete domain containing 0, 1, and ⊥; analyzing one or more output bits that are produced by an operation in terms of one or more input bits that are input to the operation; and analyzing the input bits that are input to the operation in terms of the output bits that are produced by the operation.

Abstract: A method and system for type demotion of expressions and variables by bitwise propagation is disclosed. In one embodiment, a method, comprises determining when an operation on a larger data type may be replaced by the operation on a smaller data type having a reduced precision, wherein the operation is contained in code associated with a language implementation system; and replacing the operation on the larger data type by the operation on the smaller data type.

Abstract: The invention provides a method and apparatus for optimizing code. Embodiments of the present invention comprise, for each expression in an intermediate program representation, transparently forwarding definitions of variables in said expression as said expression is being parsed by a term rewriter, the intermediate program representation being left unchanged; determining whether a term rewriting rule exists in the term rewriter for said expression; and rewriting said expression in the intermediate program representation according to said rule.

Abstract: The invention provides a method and apparatus for doing program analysis. According to embodiments of the invention program analysis comprises assigning an alias to each equivalence class of possibly overlapping memory accesses as defined by an alias analysis of an intermediate language program; and defining a definition-use relationship between statements in each equivalence class wherein definition statements which belong to the equivalence class reference the alias associated with that class, and wherein use statements which belong to the equivalence class reference the alias associated with for that class. The invention also provides a program analysis algorithm which utilizes a dependence flow graph having the property that the edge cardinality is independent of the definition-use of structure the program being analyzed.