Patents by Inventor Courtney L. Hart

Courtney L. Hart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5548875
    Abstract: A safety snap for restraining livestock that is releasable upon the application of a selected force by the animal to minimize the possibility and severity of injury to the animal and handler. A lead rope is attached to the safety snap, which is clasped to the halter. Application of a selected amount of force by the animal breaks a shear pin, unlatching the safety snap to release the lead rope. The safety snap remains attached to the halter. A reservoir in the safety snap contains replacement shear pins.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: August 27, 1996
    Inventors: Courtney L. Hart, Brian F. Tischer, David G. Lloyd
  • Patent number: 5376560
    Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide.
    Type: Grant
    Filed: January 24, 1994
    Date of Patent: December 27, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart
  • Patent number: 5372952
    Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: December 13, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart
  • Patent number: 5298435
    Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: September 3, 1992
    Date of Patent: March 29, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5280185
    Abstract: A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: January 18, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5095358
    Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: March 10, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Sung T. Ahn
  • Patent number: 5043292
    Abstract: A self-aligned masking process for use with ultra-high energy implants (implant energies equal to or greater than 1 MeV) is provided. The process can be applied to an arbitrary range of implant energies. Consequently, high doses of dopant may be implanted to give high concentrations that are deeply buried. This can be coupled with the fact that amorphization of the substrate lattice is relatively localized to the region where the ultra-high energy implant has peaked to yield a procedure to form buried, localized isolation structures.
    Type: Grant
    Filed: May 31, 1990
    Date of Patent: August 27, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Sheldon Aronowitz, Courtney L. Hart, Matthew Buynoski