Abstract: A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node.

Abstract: A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.

Abstract: Methods and apparatus are presented for scheduling playback for voice data sample packet payloads conveyed over best-effort packet-switched infrastructure. The hardware implementation presented provides support for concurrent and independent comfort noise insertion and for dynamic clock adjustment for telephone sessions provisioned concurrently without making recourse to signaling. The apparatus and methods support high density solutions scaleing up to large numbers of concurrently provisioned telephone sessions.

Abstract: A method of scheduling queue servicing in a data packet switching environment is provided. The method includes a sequence of cyclical steps. The output queues are scheduled for servicing on a least credit value basis. An output queue is selected from a group of output queues associated with a communications port. The selected output port has at least one Payload Data Unit (PDU) pending transmission and a lowest credit value associated therewith. At least one PDU having a length is transmitted from the selected output queue and the credit value is incremented taking the length of the transmitted PDU into consideration. The transmission of PDUs is divided into transmission periods. Once per transmission period credit values associated with output queues holding PDUs pending transmission are decremented in accordance with transmission apportionments assigned for each output queue. The method emulates weighted fair queue servicing with minimal computation enabling hardware implementation thereof.

Abstract: Methods and apparatus for hardware scheduling processes handling are presented. The apparatus includes a table of task lists. Each task list has specifications of processes requiring handling during a corresponding time interval. Each task list is parsed by a scheduler during a corresponding interval and the processes specified therein are handled. The methods of process handling may include a determination of a next time interval in which the process requires handling and inserting of process specifications in task lists corresponding to the determined next handling times. Implementations are also presented in which task lists specify work units requiring handling during corresponding time intervals. The entire processing power of the scheduler is used to schedule processes for handling. Advantages are derived from an efficient use of the processing power of the scheduler as the number of processes is increased.

Abstract: A method of utilizing shared memory resources in switching Protocol Data Units (PDUs) at a data switching node is presented. The method includes reserving: a temporary memory storage portion for storing PDUs prior to queuing for processing thereof, a Class-of-Service memory storage portion to provide support Quality-of-Service guarantees, a shared memory-pool portion and an input port memory storage portion enabling non-blocking input port flow control. Provisions are made for PDU discard decisions to be delayed until after PDU headers are inspected subsequent to the receipt of each PDU. Provisions are made for well-behaved data flows conveyed via an input port to be protected against blocking from misbehaving data flows conveyed via other input ports of the data switching node.

Abstract: A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node.

Abstract: A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

Abstract: A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: A system and method for implementing a control channel in a packet switched communications network. In a computer network, such as a local area network (LAN) it is known to utilize the Ethernet for distributing communications between stations. The Ethernet employs a standard frame format that includes header frames and, in particular a preamble frame which may be used to provide synchronization information between switching devices or nodes. The preamble frame is not required in a Gigabit Ethernet implementation and the present invention employs a portion of the preamble frame to implement a control channel between switching devices.

Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.

Abstract: Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.