Patents by Inventor Craig Durand Keefer

Craig Durand Keefer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write
    Patent number: 6353877
    Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity, which minimizes the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: March 5, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Samuel Hammond Duncan, Glenn Arthur Herdeg, Ricky Charles Hetherington, Craig Durand Keefer, Maurice Bennet Steinman, Paul Michael Guglielmi
  • Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
    Patent number: 6128711
    Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: October 3, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Samuel Hammond Duncan, Glenn Arthur Herdeg, Ricky Charles Hetherington, Craig Durand Keefer, Maurice Bennet Steinman, Paul Michael Guglielmi
  • Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges
    Patent number: 6012120
    Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: January 4, 2000
    Assignee: Digital Equipment Corporation
    Inventors: Samuel Hammond Duncan, Craig Durand Keefer, Thomas Adam McLaughlin, Paul Michael Guglielmi
  • Method and apparatus providing DMA transfers between devices coupled to different host bus bridges
    Patent number: 5953538
    Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity which minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read; thereby reducing the requirement of I/O reads for interrupt handling.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: September 14, 1999
    Assignee: Digital Equipment Corporation
    Inventors: Samuel Hammond Duncan, Craig Durand Keefer, Thomas Adam McLaughlin, Paul Michael Guglielmi