Abstract: A monolithic integrated circuit is provided capable of providing charge packets which are selectable multiples of other charge packets. This capability is provided by a charge-coupled device floating gate regenerator and an associated MOS capacitive region.

Abstract: A monolithic integrated circuit is provided in which signals from concurrently operating information sources are each provided to a corresponding signal processing cell in an array thereof. These cells can each communicate directly with surrounding nearest neighbor cells both to and from. Each such signal processing cell is capable of being directed in parallel to perform selected signal processing operations including operations involving data from many cells. Communications between cells can be effected using charge coupled devices, and the signal processing operations in a cell can be performed by a floating gate regenerator.

Abstract: Charge packet refreshment in a charge transfer device is performed by comparing an input charge packet to be refreshed with a reference level to form a corresponding signal and reference potential barrier and by ejecting charge from beneath a ramp electrode between said signal and reference potential barriers over the lesser of the two barriers. The area of the ramp electrode may be sufficiently large to generate refreshed charge packet of amplified size to spill over one of the two potential barriers in reponse to an input charge packet.