Abstract: A logic analyzer acquires all data and clock signal inputs asynchronously at high speed using a digital FISO (10) to produce a plurality of parallel high-speed data samples within each cycle of an internal system clock (95). The plurality of parallel high-speed data samples describe the sequential behavior of one of the input signals during one period of the internal system clock. One of the plurality of parallel high-speed data samples is then selected to be the single data sample that is stored in the acquisition memory (80) for that clock cycle. The selection process includes a skew adjustment (20), clock edge detection and selection (50), aligning the sample associated with the detected and selected clock edge to a reference location (60), and selecting (70) as the single sample to be stored a sample having a relationship to the reference location that is determined by setup and hold adjustment data.