Abstract: In some examples, a computing device may include a plurality of components, an embedded controller, and a read-only memory (ROM) to store a basic input output system (BIOS). A display device connected to the computing device may include a display panel and a timing controller. The embedded controller may be configured with instructions to determine that a power-on has been initiated, determine that a particular component of the plurality of components of the computing device has an issue that prevents booting the BIOS, and send a message from the embedded controller to the timing controller. The message may instruct the timing controller to display, on the display panel and before the CPU begins execution, one or more error messages associated with the particular component that has the issue preventing booting the BIOS. In some cases, a logo may be displayed along with the one or more error messages.

Abstract: Motherboard connector failures can be predicted. An embedded controller can be employed on the motherboard to monitor when devices are connected to and disconnected from the motherboard's connectors. The embedded controller can maintain an event log and connector information in which it counts the number of times a device is connected to/disconnected from a connector. The BIOS can leverage the event log and the connector information to notify an end user to take action to correct or prevent possible corrosion. Training records may also be employed to predict connector failure. The training records can track and maintain baseline and periodic device training attributes. When the periodic training attributes deviate from the baseline training attributes, an end user can be notified to take action to remove corrosion.

Abstract: A system, method, and computer-readable medium are disclosed for securing hot-pluggable ports, such as USB ports, of an information handling system, by isolating a dedicated controller from the operating system of the information handling system. Devices that are to be allowed to be enabled at the ports are determined. A hash signature is created and saved to verify the devices. The controller and ports are held in reset until the devices are authenticated.

Abstract: Detecting failures using power consumption profiling, including calibrating, at a first time, a system power profile of an information handling system (IHS), including identifying an initial baseline current value of a backlight power of a display device of the IHS; identifying an initial baseline current value of a timing controller of the IHS; calculating, at a second time, an updated system power profile, including: identifying an updated current value of the backlight power of the display device of the IHS; identifying an updated current value of the timing controller of the IHS; determining whether the updated current value of the backlight power of the display device is within a threshold value of the initial baseline current value of the backlight power of the display device.

Abstract: A system, method, and computer-readable medium are disclosed for securing hot-pluggable ports, such as USB ports, of an information handling system, by isolating a dedicated controller from the operating system of the information handling system. Devices that are to be allowed to be enabled at the ports are determined. A hash signature is created and saved to verify the devices. The controller and ports are held in reset until the devices are authenticated.

Abstract: Motherboard connector failures can be predicted. An embedded controller can be employed on the motherboard to monitor when devices are connected to and disconnected from the motherboard's connectors. The embedded controller can maintain an event log and connector information in which it counts the number of times a device is connected to/disconnected from a connector. The BIOS can leverage the event log and the connector information to notify an end user to take action to correct or prevent possible corrosion. Training records may also be employed to predict connector failure. The training records can track and maintain baseline and periodic device training attributes. When the periodic training attributes deviate from the baseline training attributes, an end user can be notified to take action to remove corrosion.

Abstract: An information handling system embedded controller does not initiate a chipset having secure execution of chipset firmware unless the chipset firmware validates against error correcting checksums inserted into the embedded controller firmware. Comparing checksums calculated from chipset firmware against expected checksum values for the chipset firmware prevents secure chipset initiation failure due to bit errors associated with chipset firmware storage in flash memory.

Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.

Abstract: A method may include, during a boot of an information handling system, detecting a soft failure associated with a read request to storage media of the information handling system wherein the soft failure is not visible to an operating system of the information handling system and in response to detecting the soft failure, rewriting a sector of the storage media affected by the soft failure to correct the soft failure.

Abstract: An information handling system may include a processor, an information handling resource communicatively coupled to the processor, and an electrical margining module communicatively coupled to the processor. The electrical margining module may be configured to, during a boot of the information handling system, determine whether a condition has occurred for electrically re-margining the information handling resource, and responsive to determining that the condition has occurred, determine a new receiver equalization setting for receiving signals from the information handling resource and determine a new driver pre-emphasis setting for transmitting signals to the information handling resource.

Abstract: In some examples, a computing device may include a plurality of components, an embedded controller, and a read-only memory (ROM) to store a basic input output system (BIOS). A display device connected to the computing device may include a display panel and a timing controller. The embedded controller may be configured with instructions to determine that a power-on has been initiated, determine that a particular component of the plurality of components of the computing device has an issue that prevents booting the BIOS, and send a message from the embedded controller to the timing controller. The message may instruct the timing controller to display, on the display panel and before the CPU begins execution, one or more error messages associated with the particular component that has the issue preventing booting the BIOS. In some cases, a logo may be displayed along with the one or more error messages.

Abstract: A method may include, during a boot of an information handling system, detecting a soft failure associated with a read request to storage media of the information handling system wherein the soft failure is not visible to an operating system of the information handling system and in response to detecting the soft failure, rewriting a sector of the storage media affected by the soft failure to correct the soft failure.

Abstract: An information handling system may include a processor, an information handling resource communicatively coupled to the processor, and an electrical margining module communicatively coupled to the processor. The electrical margining module may be configured to, during a boot of the information handling system, determine whether a condition has occurred for electrically re-margining the information handling resource, and responsive to determining that the condition has occurred, determine a new receiver equalization setting for receiving signals from the information handling resource and determine a new driver pre-emphasis setting for transmitting signals to the information handling resource.

Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.

Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.

Abstract: An information handling system embedded controller does not initiate a chipset having secure execution of chipset firmware unless the chipset firmware validates against error correcting checksums inserted into the embedded controller firmware. Comparing checksums calculated from chipset firmware against expected checksum values for the chipset firmware prevents secure chipset initiation failure due to bit errors associated with chipset firmware storage in flash memory.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may receive, via a light sensor, multiple light transmissions from an information handling system, the multiple light transmissions including multiple light sequences, where at least one light sequence of the multiple light sequences includes at least two different colors; may determine respective multiple colors of the multiple light transmissions; may determine the multiple color sequences from the multiple colors; may determine information represented by the multiple color sequences based at least on content and ordering of the multiple color sequences; and may provide the information to a service entity via a network.

Abstract: Disclosed herein are methods, systems, and processes to embed forensic and triage data in memory dumps. Memory dump data being written to kernel memory of a computing system by a firmware interface is detected. An operating mode of an operating system executing on the computing system is activated. Hardware forensic data is generated by reading local computer bus data, firmware event log data, and memory mapped input/output (I/O) data associated with the computing system. The hardware forensic data is then stored in a memory location of the kernel memory, causing the hardware forensic data to be included in the memory dump data being written to kernel memory.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may receive, via a light sensor, multiple light transmissions from an information handling system, the multiple light transmissions including multiple light sequences, where at least one light sequence of the multiple light sequences includes at least two different colors; may determine respective multiple colors of the multiple light transmissions; may determine the multiple color sequences from the multiple colors; may determine information represented by the multiple color sequences based at least on content and ordering of the multiple color sequences; and may provide the information to a service entity via a network.

Abstract: Disclosed herein are methods, systems, and processes to embed forensic and triage data in memory dumps. Memory dump data being written to kernel memory of a computing system by a firmware interface is detected. An operating mode of an operating system executing on the computing system is activated. Hardware forensic data is generated by reading local computer bus data, firmware event log data, and memory mapped input/output (I/O) data associated with the computing system. The hardware forensic data is then stored in a memory location of the kernel memory, causing the hardware forensic data to be included in the memory dump data being written to kernel memory.