Abstract: In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.

Abstract: A method for rendering a plurality of line primitives. The method includes the step of accessing a first line primitive and a second line primitive of a line strip. For a junction between the first line primitive and the second line primitive, the first line primitive and the second line primitive are geometrically modified to generate an abutting edge between the first line primitive and the second line primitive. A majority status is assigned to a pixel on the abutting edge. A first color of the first line primitive or a second color of the second line primitive is allocated to the pixel in accordance with the majority status.

Abstract: The present invention relates to a traffic generator and a method for testing the performance of the memory system of graphic processing unit. The traffic generator comprises: at least one simulated engine module, each for generating at least one read stream and/or at least one write stream; and an output arbiter for selecting a stream to be output from a group comprising the at least one read stream and/or the at least one write stream; wherein the selected stream is arranged to be output to the memory system of graphic processing unit.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

Abstract: In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.

Abstract: Graphics processing devices and methods are provided for culling small primitives that do not cover any pixels. A boundary (e.g., a diamond) is defined around a pixel center, with pixel coverage being determined for some types of primitives based on whether the boundary is crossed. The boundaries divide the raster into internal regions and external regions. Each region is assigned a unique canonical identifier. Each vertex of a primitive is assigned the canonical identifier corresponding to the region that contains that vertex. The canonical coordinates of the vertices are used to cull primitives that do not satisfy the boundary crossing coverage rules for any pixels.

Abstract: Clipping techniques introduce additional vertices into existing primitives without requiring creation of new primitives. For an input triangle with one vertex on the invisible side of a clipping surface, a quadrangle can be defined. The vertices of the quadrangle are the two internal vertices of the input triangle and two clipped vertices. For determining attribute values for pixel shading, three vertices of the quadrangle are selected, and a parameter value for an attribute equation is computed using the three selected vertices. For determining pixel coverage for the quadrangle, the three edges that do not correspond to the edge created by clipping are used.

Abstract: A sort middle graphics architecture comprising a host interface for receiving raw primitive data from a graphics application; a geometry processing module coupled to the host interface for receiving the raw primitive data from the host interface and generating sort middle traffic data, said geometry processing module a having a built-in compression module for compressing the sort middle traffic data; and a rasterization module coupled to the host interface for receiving the compressed sort middle traffic data and rasterizing the data, said rasterization module having a built-in decompression module for decompressing the sort middle traffic data before it is rasterized.

Abstract: An apparatus for semiautomatic classification of volume data provides the ability to generate visually significant representations of the important regions of the data set. The representations may be indicated by opacity or color changes, for example. The apparatus comprises programming to compute a two-dimensional (2D) histogram over a volume of scalar values, ƒ, versus edge values edge( ). A common edge value is the gradient magnitude, edge ( )=|?ƒ|.

Abstract: A geometry compression method for sort middle, screen space, graphics of the standard graphics pipeline. The pipeline processes a 3D database having geometric objects such as triangles and textures into a display image which may be shown to the user on a display monitor. Lossless compression is achieved through redundancy elimination. Triangles are processed following their transformation to screen space, so that the vertex world 3D locations are determined in their projection to the screen 2D locations. Triangles may also be processed by back projecting the screen space scanlines to test locations against the world space triangles. The general technique is to identify the portions of the data that have little or no effect on the rendered output and remove them during compression. Specific examples disclosed include full packing, constant color, delta coding, edge sharing, slope coding, and color quantization.

Abstract: An apparatus for semiautomatic classification of volume data provides the ability to generate visually significant representations of the important regions of the data set. The representations may be indicated by opacity or color changes, for example. The apparatus comprises programming to compute a two-dimensional (2D) histogram over a volume of scalar values, f, versus edge values edge( ). A common edge value is the gradient magnitude, edge ( )=|∇f|.

Abstract: A geometry compression method for sort middle, screen space, graphics of the standard graphics pipeline. The pipeline processes a 3D database having geometric objects such as triangles and textures into a display image which may be shown to the user on a display monitor. Lossless compression is achieved through redundancy elimination. Triangles are processed following their transformation to screen space, so that the vertex world 3D locations are determined in their projection to the screen 2D locations. Triangles may also be processed by back projecting the screen space scanlines to test locations against the world space triangles. The general technique is to identify the portions of the data that have little or no effect on the rendered output and remove them during compression. Specific examples disclosed include full packing, constant color, delta coding, edge sharing, slope coding, and color quantization.

Abstract: A sort middle graphics architecture comprising a host interface for receiving raw primitive data from a graphics application; a geometry processing module coupled to the host interface for receiving the raw primitive data from the host interface and generating sort middle traffic data, said geometry processing module a having a built-in compression module for compressing the sort middle traffic data; and a rasterization module coupled to the host interface for receiving the compressed sort middle traffic data and rasterizing the data, said rasterization module having a built-in decompression module for decompressing the sort middle traffic data before it is rasterized.

Abstract: Texture mapping computer graphics apparatus includes an associating interpolator circuit for determining first interpolated opacity weighted colors and a first interpolated opacity in response to texture coordinates and texture colors and corresponding texture opacities, an associated color compositing circuit for a compositing the first interpolated opacity weighted colors and second interpolated opacity weighted colors to provide new opacity weighted colors, an associated opacity compositing circuit for compositing the first interpolated opacity and a second interpolated opacity to provide a new opacity, an unassociating circuit responsive to the new opacity weighted colors and the new opacity for providing unassociated colors, and a frame buffer for storing the unassociated new colors and the new opacity.

Abstract: This disclosure provides a rendering device that blends overlapping fragments via a hardware ordering of those fragments. The preferred device uses a fragment buffer, two depth storages and a frame buffer. In back-to-front rendering, any closest opaque or furthest transparent data is found and stored on the frame buffer. Then, one depth storage is used to hold the depth of next furthest transparent data. In a subsequent pass, the held depth is used to retrieve and process a fragment from the fragment buffer while the second depth storage is simultaneously used to identify the next furthest depth for other fragments. Usage of the depth storages is then switched in each subsequent pass. This disclosure also provides implementations compatible with front-to-back composition, antialiasing, deferred shading and pipeline architecture.

Abstract: A plurality of program processors, shared memory, dual port memory, external cache memory and a control processor form a multiprocessor system. A shared memory bus links the program processors, shared memory, dual port memory and external cache memory. Program processor I/O occurs through a pair of serial I/O channels coupled to one port of the dual port memory. A write generate mode is implemented for updating cache by first allocating lines of shared memory as write before read areas. For such lines, cache tags are updated directly on cache misses without reading from memory. A hit is forced for such line, resulting in valid data at the updated part and invalid data at the remaining portion. Thus, part of the line is written to and the rest invalidated. The invalid portions are not read, unless preceded by a write operation. The mode reduces the number of bus cycles by making write misses more efficient.