Abstract: The present invention relates to methods of synthesizing long-chain polyunsaturated fatty acids, especially eicosapentaenoic acid, docosapentaenoic acid and docosahexaenoic acid, in recombinant cells such as yeast or plant cells. Also provided are recombinant cells or plants which produce long-chain polyunsaturated fatty acids. Furthermore, the present invention relates to a group of new enzymes which possess desaturase or elongase activity that can be used in methods of synthesizing long-chain polyunsaturated fatty acids. In particular, the present invention provides ?3 destaurases, ?5 elongases and ?6 desaturases with novel activities. Also provided are methods and DNA constructs for transiently and/or stably transforming cells, particularly plant cells, with multiple genes.

Abstract: The present invention relates to methods of synthesizing long-chain polyunsaturated fatty acids, especially eicosapentaenoic acid, docosapentaenoic acid and docosahexaenoic acid, in recombinant cells such as yeast or plant cells. Also provided are recombinant cells or plants which produce long-chain polyunsaturated fatty acids. Furthermore, the present invention relates to a group of new enzymes which possess desaturase or elongase activity that can be used in methods of synthesizing long-chain polyunsaturated fatty acids. In particular, the present invention provides ?3 desaturases, ?5 elongases and ?6 desaturases with novel activities. Also provided are methods and DNA constructs for transiently and/or stably transforming cells, particularly plant cells, with multiple genes.

Abstract: The present invention relates to methods of synthesizing long-chain polyunsaturated fatty acids, especially eicosapentaenoic acid, docosapentaenoic acid and docosahexaenoic acid, in recombinant cells such as yeast or plant cells. Also provided are recombinant cells or plants which produce long-chain polyunsaturated fatty acids. Furthermore, the present invention relates to a group of new enzymes which possess desaturase or elongase activity that can be used in methods of synthesizing long-chain polyunsaturated fatty acids. In particular, the present invention provides ?3 destaurases, ?5 elongases and ?6 desaturases with novel activities. Also provided are methods and DNA constructs for transiently and/or stably transforming cells, particularly plant cells, with multiple genes.

Abstract: The present invention relates to methods of synthesizing long-chain polyunsaturated fatty acids, especially eicosapentaenoic acid, docosapentaenoic acid and docosahexaenoic acid, in recombinant cells such as yeast or plant cells. Also provided are recombinant cells or plants which produce long-chain polyunsaturated fatty acids. Furthermore, the present invention relates to a group of new enzymes which possess desaturase or elongase activity that can be used in methods of synthesizing long-chain polyunsaturated fatty acids. In particular, the present invention provides ?3 destaurases, ?5 elongases and ?6 desaturases with novel activities. Also provided are methods and DNA constructs for transiently and/or stably transforming cells, particularly plant cells, with multiple genes.

Abstract: The present invention relates generally to the field of recombinant fatty acid synthesis, particularly in transgenic plants. The application describes genes involved in fatty acid synthesis and provides methods and vectors for the manipulation of fatty acid composition of plant oils. In particular, the invention provides constructs for achieving the integration of multiple heterologous genes involved in fatty acid synthesis into the plant genome, such that the resulting plants produce altered levels of polyunsaturated fatty acids. Also described are methods for enhancing the expression of fatty acid biosynthesis enzymes by co-expressing a silencing suppressor within the plant storage organ.

Abstract: The present invention is directed to a gypsum panel and a method of making such gypsum panel. For instance, in one embodiment, the gypsum panel comprises a gypsum core and a first facing material and a second facing material sandwiching the gypsum core, wherein the gypsum core includes gypsum and one or more components of a reclaim gypsum panel, such as reclaimed gypsum and reclaimed facing material. The methods of the present invention are directed to making the aforementioned gypsum panels by providing the first facing material, providing a gypsum slurry comprising gypsum, water, and one or more components of a reclaim gypsum panel, such as reclaimed gypsum and reclaimed facing material, onto the first facing material, and providing a second facing material on the gypsum slurry.

Abstract: The present invention is directed to a gypsum panel and a method of making such gypsum panel. For instance, in one embodiment, the gypsum panel comprises a gypsum core and a first facing material and a second facing material sandwiching the gypsum core, wherein the gypsum core includes gypsum and one or more carbon sequestration additives. The methods of the present invention are directed to making the aforementioned gypsum panels by providing the first facing material, providing a gypsum slurry comprising gypsum, water, and one or more carbon sequestration additives onto the first facing material, and providing a second facing material on the gypsum slurry.

Abstract: Systems, methods, and computer-readable media are described for compact radar systems. In some examples, a compact radar system can include a first set of transmit antennas, a second set of receive antennas, one or more processors, and at least one computer-readable storage medium storing computer-executable instructions which, when executed by the one or more processors, cause the radar system to coordinate digital beam steering of the first set of transmit antennas and the second set of receive antennas, and coordinate digital beam forming with one or more of the second set of receive antennas to detect one or more objects within a distance of the radar system.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: The present invention is directed to a gypsum panel and a method of making a gypsum panel. The gypsum panel comprises a gypsum core and a facing material. The gypsum core includes gypsum, a foaming agent, and optionally starch in an amount of less than 4 wt. % based on the weight of gypsum. The gypsum core includes air voids having an average void size of 50 microns or more. The gypsum panel has a density of 33 pcf or less, a weight of 1,800 lbs/MSF or less, and an NRC value of 0.2 or more.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A package has a plurality of seamless compartments coupled together. A different one of the plurality compartments each includes a different respective one of a plurality of respective void spaces and a different respective one of a plurality of respective void space delimiting surfaces. A different one of a plurality of fill entries each forms a fluent entry into a different respective compartment's void space. At least one fill entry of said plurality is in an elastomeric portion of said package, and the at least one fill entry has a largest cross sectional area which is equal to or less than 25% of a largest cross sectional area of the compartment having the respective void space for which the fill entry forms the fluent entry. Each void space delimiting surface follows an outline of a separate 3D pill shape.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.