Abstract: An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit communicates in parallel with the ATM layer, and the second circuit communicates in parallel with the PHY layer. The extender circuit additionally includes a serial link which serially transmits signals between the first and second circuits. The serial link includes a first serial link for transmitting a first serial signal from the first circuit to the second circuit, and a second serial link transmitting a second serial signal from the second circuit to the first circuit. The first circuit and the second circuit include similar architecture. The first circuit includes a parallel interface circuit for communicating in parallel with the ATM layer and a serial interface circuit coupled to the parallel interface circuit for serially communicating with the second circuit.

Abstract: An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit is coupled to the ATM layer and communicates in parallel with the ATM layer. The first circuit is operable to receive a control signal from the ATM layer. The second circuit is coupled to the PHY layer and communicates in parallel with the PHY layer. The first circuit does not transmit the control signal to the second circuit. The second circuit regenerates the control signal at the PHY layer. The first circuit and the second circuit function in like manners. The first circuit receives a control signal generated by the ATM layer. The control signal may comprise a start of cell signal. The first circuit transmits a first sequence of signals to the second circuit.