Abstract: The invention, in its various aspects and embodiments, is a method and apparatus for controlling the operation of a multi-chamber process tool in a semiconductor fabrication process. The method comprises setting a plurality of operation parameters for the conduct of a predetermined operation in each of a plurality of process chambers in a multi-chamber process tool; performing the predetermined operation in each of the process chambers; examining a physical characteristic of a processed wafer from each of the process chambers; determining from the examined physical characteristics whether the operating conditions in each of the process chambers match; and resetting at least one operating parameter so that the operating conditions in each of the process chambers will match. The apparatus comprises a processing tool, a review station, and a tool controller. The processing tool includes a plurality of process chambers and an operation controller.

Abstract: A method and an apparatus for controlling a deposition process in a manufacturing process. A process recipe setting step is performed. A process run of semiconductor devices is performed based upon the process recipe. Metrology data relating to the process run of semiconductor dev determination is made whether production results are within a predetermined tolerance level, based upon the metrology data. Process recipe settings are modified in response to a determination that the production results are within a predetermined tolerance level, based upon the metrology data. A processing tool is capable of receiving at least one control input parameter and a metrology data acquisition unit is interfaced with the processing tool and is capable of acquiring metrology data from the processing tool.

Abstract: A method for reducing deposition thickness variation in a processing tool comprises storing a post-clean performance model of the processing tool; receiving at least one of a showerhead age and a tool idle time associated with the processing tool as an input parameter; determining temperature control parameters based on the input parameter and the post-clean performance model; and modifying an operating recipe of the processing tool based on the temperature control parameters. A processing system includes a processing tool and an automatic process controller. The processing tool is adapted to process wafers in accordance with an operating recipe.

Abstract: A processing line includes a processing tool, a measurement tool, and an automatic process controller. The processing tool is adapted to process articles. The measurement tool is adapted to measure a characteristic of selected articles at a measurement frequency. The automatic process controller is adapted to change the measurement frequency based on a usage characteristic of the processing tool. A method for monitoring a processing tool includes processing a plurality of articles in the processing tool; measuring a characteristic of selected articles at a measurement frequency; and changing the measurement frequency based on a usage characteristic of the processing tool.

Abstract: A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

Abstract: A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

Abstract: A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.

Abstract: A field oxide is provided which purposefully takes advantage of fluorine mobility from an implanted impurity species. The field oxide can be enhanced or thickened according to the size (area and thickness) of the oxide. Fluorine from the impurity species provides for dislodgement of oxygen at silicon-oxygen bond sites, leading to oxygen recombination at the field oxide/substrate interface. Thickening of the oxide through recombination occurs after it is initially grown and implanted. Accordingly, initial thermal oxidation can be shortened to enhance throughput. The fluorine-enhanced thickening effect can therefore compensate for the shorter thermal oxidation time. Moreover, the thickened oxide regions are anistropically oxidized underneath existing thermally grown oxides and directly underneath openings between nitrides. The thickened oxides therefore do not cause additional shrinkage of the active areas which reside between field oxides.

Abstract: An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method advantageously places a film of metal nitride upon the metal layer. The metal nitride layer and metal layer are sputter deposited within the same chamber without removing the substrate from the vacuum so as to prevent oxygen or moisture from contaminating the metal layer and causing oxides to form thereon. Furthermore, the metal nitride layer is reactively sputter deposited in a nitrogen/argon ambient to allow precise amounts of nitrogen to be deposited across uneven surface topography directly adjacent to the underlying metal layer. Excess nitrogen purposefully deposited within the metal nitride layer consumes a controlled depth of metal bond sites within the underlying metal layer so as to limit the amount of silicidation from underlying silicon or polysilicon into the metal thereby substantially eliminating or minimizing silicide shorting problems.

Abstract: An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method utilizes ion beam mixing by implanting germanium to a specific elevation level within a metal layer overlying a silicon contact region. The implanted germanium atoms impact upon and move a plurality of metal atoms through the metal-silicon interface and into a region residing immediately below the silicon (or polysilicon) surface. The metal atoms can therefore bond with silicon atoms to cause a pre-mixing of metal with silicon near the interface in order to enhance silicidation. Germanium is advantageously chosen as the irradiating species to ensure proper placement of the germanium and ensuing movement of dislodged metal atoms necessary for minimizing oxides left in the contact windows and lattice damage within the underlying silicon (or polysilicon).

Abstract: A method is provided for controlling growth of silicide to a defined thickness based upon the relative position of peak concentration density depth within a layer of titanium. The titanium layer is deposited over silicon and namely over the silicon junction regions. Thereafter the titanium is implanted with argon ions. The argon ions are implanted at a peak concentration density level corresponding to a depth relative to the upper surface of the titanium. The peak concentration density depth can vary depending upon the dosage and implant energies of the ion implanter. Preferably, the peak concentration density depth is at a midpoint between the upper and lower surfaces of the titanium or at an elevational level beneath the midpoint and above the lower surface of the titanium. Subsequent anneal of the argon-implanted titanium causes the argon atoms to occupy a diffusion area normally taken by silicon consumed and growing within overlying titanium.

Abstract: A method is provided for reducing growth of silicide and the temperatures necessary to produce silicide. Germanium is implanted at a concentration peak density depth below the midline and above the lower surface of a metal layer receiving the implant. Subsequent anneal causes germanide to occupy an area above growing silicide such that consumption of silicon atoms is reduced, and that silicide is formed to a controlled thickness.

Abstract: A PMOS device is provided having a diffusion barrier placed within a polysilicon gate material. The diffusion barrier is purposefully implanted to a deeper depth within the gate material than subsequently placed impurity dopants. The barrier comprises Ar atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises ions of BF.sub.2. F from the impurity dopant of BF.sub.2 is prevented from diffusing to underlying silicon-oxide bonds residing within the oxide bulk. By minimizing F migration to the bond sites, the present polysilicon barrier and method of manufacture can minimize oxygen dislodgment and recombination at the interface regions between the polysilicon and the gate oxide as well as between the gate oxide and silicon substrate.

Abstract: A field oxide is provided which purposefully takes advantage of fluorine mobility from an implanted impurity species. The field oxide can be enhanced or thickened according to the size (area and thickness) of the oxide. Fluorine from the impurity species provides for dislodgement of oxygen at silicon-oxygen bond sites, leading to oxygen recombination at the field oxide/substrate interface. Thickening of the oxide through recombination occurs after it is initially grown and implanted. Accordingly, initial thermal oxidation can be shortened to enhance throughput. The fluorine-enhanced thickening effect can therefore compensate for the shorter thermal oxidation time. Moreover, the thickened oxide regions are anistropically oxidized underneath existing thermally grown oxides and directly underneath openings between nitrides. The thickened oxides therefore do not cause additional shrinkage of the active areas which reside between field oxides.