Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

Abstract: Methods, apparatus, systems and articles of manufacture to perform region formation for usage by a dynamic binary translation are disclosed. An example apparatus includes an initial region former to form an initial region starting at a first block of hot code of a control flow graph. The initial region former also adds blocks of hot code lying on a first hottest path of the control flow graph. A region extender extends the initial region to form an extended region including the initial region. The extended region begins at a hottest exit of the initial region and includes blocks of hot code lying on a second hottest path until one of a threshold path length has been satisfied or a back edge of the control flow graph is added to the extended region. A region pruner prunes the remove all loop nests except a selected loop nest which forms a final region.

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Abstract: A processor comprising an instruction execution circuit to execute a translated code generated based on a received code and a translation table (TT) controller circuit coupled to a translation table comprising a plurality of address mappings, wherein the TT controller circuit is to identify a trigger event associated with a physical memory page, determine, based on an identifier of the physical memory page, an entry in a manifest table, the entry comprising an address mapping between a first memory address within an address range comprising the physical memory page and a second memory address, and store the address mapping to the translation table.

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

Abstract: Methods, apparatus, systems and articles of manufacture to perform region formation for usage by a dynamic binary translation are disclosed. An example apparatus includes an initial region former to form an initial region starting at a first block of hot code of a control flow graph. The initial region former also adds blocks of hot code lying on a first hottest path of the control flow graph. A region extender extends the initial region to form an extended region including the initial region. The extended region begins at a hottest exit of the initial region and includes blocks of hot code lying on a second hottest path until one of a threshold path length has been satisfied or a back edge of the control flow graph is added to the extended region. A region pruner prunes the remove all loop nests except a selected loop nest which forms a final region.

Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.

Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.

Abstract: Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises determining whether a condition is met and serializing an operation of a first thread of a multi-threaded program relative to an operation of a second thread of the multi-threaded program. The serialization of the operations of the first and second threads results in a concurrency violation or bug thereby causing the multi-threaded program to crash. In this way, the operations of the first and second threads of the multi-threaded program that are responsible for the concurrency violation are identified and can be revised to remove the bug.