Patents by Inventor Curtis Gene Garrett

Curtis Gene Garrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermoplastic mounting of a semiconductor die to a substrate having a mismatched coefficient of thermal expansion
    Patent number: 6127203
    Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.
    Type: Grant
    Filed: May 5, 1999
    Date of Patent: October 3, 2000
    Assignee: DRS Technologies, Inc.
    Inventors: Chang-Feng Wan, Richard Scott List, Curtis Gene Garrett, Dwight U. Bartholomew
  • Thermoplastic mounting of a semiconductor die to a substrate having a mismatched coefficient of thermal expansion
    Patent number: 5959340
    Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: September 28, 1999
    Assignee: DRS Technologies, Inc.
    Inventors: Chang-Feng Wan, Richard Scott List, Curtis Gene Garrett, Dwight U. Bartholomew