Abstract: A full bisection bandwidth network, having a plurality of nodes and a plurality of paths among the nodes, is divided into a plurality of Virtual Local Area Networks (“VLANs”) by assigning paths to the VLANs such that each VLAN satisfies a spanning tree protocol and all paths are active in at least one VLAN.

Abstract: The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites.

Abstract: The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites.

Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (?-field) results from the changing dopant concentration. The creation of this ?-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.

Abstract: The present invention is directed to a built-in solution for soft error protection by forming an epitaxial layer with a graded dopant concentration. By grading a dopant concentration, starting from a first dopant concentration and ending with a second dopant concentration at the device layer, usually determined by the characteristics of the device to be built in the device layer, a constant electric field (&egr;-field) results from the changing dopant concentration. The creation of this &egr;-field influences the stray, unwanted charges (or transient charges) away from critical device components. Charges that are created in the epitaxial layer are sweep downward, toward, and sometimes into, the substrate where they are absorbed, thus unable to cause a soft error in the device.

Abstract: An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel protocol (FCP) commands are implemented according to ATM standards to provide communication with peripherals. A segmentation and reassembly (SAR) unit is provided for performing ATM segmentation and reassembly. The SAR includes functional units which allow direct connection of an application agent to the core of the switch once the cell characteristics are determined by the application agent and provides ATM cell translation to and from available kernel buffers. The transmission media in the ATM network comprises digital optical links. The enhanced ATM switch may also include a synchronous optical network (SONET) interface for providing SONET transmission over the digital optical links in the ATM network.