Patents by Inventor Curtis N. Potter

Curtis N. Potter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040185323
    Abstract: A fuel cell structure and method of manufacture is disclosed that enables very low cost fabrication using conventional semiconductor manufacturing facilities. The fuel cell structure permits fabrication of all the salient features on a single planar substrate. Current extractor lines, electrodes, catalyst, proton exchange membrane, fuel and oxidizer channels and manifolds, electrical interconnect between cells, and end caps are all fabricated sequentially through additive and subtractive processing on a single substrate. The structure provides for ion exchange membrane conduction to take place perpendicular to the plane of the cell. The design and manufacturing technique allows for the production of a very small elemental cell with high power density. The monolithic structure provides for the stacking of the elemental cells or entire interconnected substrates by virtue of built-in fuel and oxidizer manifold chambers and electrical interconnect fabricated within each elemental cell.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Inventors: Burt W. Fowler, Daniel B. Bullock, Curtis N. Potter
  • Publication number: 20040115507
    Abstract: A fuel cell structure and method of manufacture is disclosed that enables very low cost fabrication using conventional semiconductor manufacturing facilities. The fuel cell structure permits fabrication of all the salient features on one side of a single planar substrate. Electrical current extractor lines, electrodes with catalyst, proton exchange membrane, fuel and oxidizer channels, manifolds for each cell and channeled cover plate are all fabricated sequentially through additive and subtractive processing on one side of a planar substrate. The structure provides for ion exchange membrane conduction to take place parallel to the plane of the cell. The design and manufacturing technique allows for the production of a very small elemental cell with high power density. The monolithic structure provides for the stacking of the elemental cells or entire interconnected substrates by virtue of built in fuel and oxidizer manifold chambers fabricated within each elemental cell.
    Type: Application
    Filed: December 3, 2003
    Publication date: June 17, 2004
    Inventors: Curtis N. Potter, Daniel B. Bullock, Burt W. Fowler
  • Patent number: 5347086
    Abstract: A coaxial bump for connecting a die to a substrate includes a center post and a ground ring surrounding and shielding the center post. The center post may be a center conductor line, and the ground ring may be generally torus-shaped, nearly closed or completely closed. The coaxial bump provides very low crosstalk in chip-to-substrate interconnections and provides a constant impedance with negligible inductive discontinuity.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: September 13, 1994
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Curtis N. Potter, David A. Gibson, Uttam S. Ghoshal
  • Patent number: 4922323
    Abstract: A method for producing miniature, planar, hermetically sealed, electrical feedthrus having multiple layers of molybdenum conductors separated by aluminum which is anodized and selectively etched for providing supports for the multilayer. The exposed molybdenum is cleaned and oxidized and sealed with glass to provide a hermetic seal. Contact portions of the molybdenum are cleaned and plated whereby the contacts will accept a contact seal.
    Type: Grant
    Filed: February 1, 1988
    Date of Patent: May 1, 1990
    Assignee: Microelectronics and Computer Technology Corporation
    Inventor: Curtis N. Potter
  • Patent number: 4899439
    Abstract: A high density electrical interconnect having a plurality of metallic conductors supported from metallic pillars which are electrically isolated from the ground plane by openings. The interconnect can be fabricated using a temporary support dielectric, which may be removed after completion to provide an air dielectric or be replaced with a more suitable permanent dielectric. The removal of the temporary support allows the conductors to be coated with protective layers or with a layer of a higher conductivity.
    Type: Grant
    Filed: June 15, 1989
    Date of Patent: February 13, 1990
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Curtis N. Potter, Lawrence N. Smith, Harry Kroger
  • Patent number: 4794021
    Abstract: Applying a photoresist layer containing a solvent to the top of an electronic wafer by spin coating. Before the layer dries the wafer is heated in an oven while controlling the solvent loss from the coating by maintaining the pressure of the solvent vapor and providing a slow solvent loss for planarizing the top surface of the polymer. The device is removed from the first oven and the bake cycle is completed in a standard convection bake oven.
    Type: Grant
    Filed: November 13, 1986
    Date of Patent: December 27, 1988
    Assignee: Microelectronics And Computer Technology Corporation
    Inventor: Curtis N. Potter
  • Patent number: 4747908
    Abstract: A method for producing miniature, planar, hermetically sealed, electrical feedthrus having multiple layers of molybdenum conductors separated by aluminum which is anodized and selectively etched for providing supports for the multilayer. The exposed molybdenum is cleaned and oxidized and sealed with glass to provide a hermetic seal. Contact portions of the molybdenum are cleaned and plated whereby the contacts will accept a contact seal.
    Type: Grant
    Filed: April 9, 1987
    Date of Patent: May 31, 1988
    Assignee: Microelectronics and Computer Technologogy Corporation
    Inventor: Curtis N. Potter
  • Patent number: 4681666
    Abstract: A planarization method of fabricating a layer of metal conductors embedded in a dielectric level. A coating of aluminum is anodized from the top but leaving a thickness of unanodized aluminum on the bottom. The top is masked and etched to provide a predetermined bare area which is etched out down to the unanodized aluminum. A metal is plated to the unanodized aluminum equal to the thickness of the unexposed anodic aluminum. The mask is removed and the unanodized aluminum is anodized. Therefore, the layer of metal and the dielectric anodic aluminum are planarized. Another anodizable metal may be used as an undercoat layer for completing the anodizing of the aluminum.
    Type: Grant
    Filed: November 13, 1986
    Date of Patent: July 21, 1987
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Curtis N. Potter, Harry Kroger
  • Patent number: 4681655
    Abstract: A method of fabricating an anodic aluminum support system having an air bridge for metallic conductors. The method includes providing two or more metal layers separated by a coating of aluminum creating a multiple layer electrical interconnect system. The method includes the step of anodizing the aluminum and applying a photoresist mask to spaced portions of the top of the system. Thereafter, an etching solution is applied to the top of the system for removing the anodized aluminum, except for the portions covered by the mask, thereby providing a multilayer conductor system supported by pillars of anodic aluminum surrounded by low dielectric air.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: July 21, 1987
    Assignee: Microelectronics and Computer Technology Corporation
    Inventor: Curtis N. Potter