Abstract: A system and method of providing a protective cover to occupants of a room, which includes detecting an occurrence of a threatening event with a protection system deployed in the room, such as detecting gunfire with the protection system and/or receiving a transmitted command of the threatening event by the protection system, and emitting an obscuring haze into the room from a haze generator of the protection system in response to the detected occurrence of the gunfire. The emitted obscuring haze obscures the light of sight contact between a shooter and the occupants in the room, which provides a measure of cover for the occupants while other assistance is being organized. This reduces the chances that the shooter will be able to accurately shoot any victim, increasing the odds of victim survival.

Abstract: A system and method of providing a protective cover to occupants of a room, which includes detecting an occurrence of a threatening event with a protection system deployed in the room, such as detecting gunfire with the protection system and/or receiving a transmitted command of the threatening event by the protection system, and emitting an obscuring haze into the room from a haze generator of the protection system in response to the detected occurrence of the gunfire. The emitted obscuring haze obscures the light of sight contact between a shooter and the occupants in the room, which provides a measure of cover for the occupants while other assistance is being organized. This reduces the chances that the shooter will be able to accurately shoot any victim, increasing the odds of victim survival.

Abstract: A simulation engine for logically simulating a logic network, which is divided into several levels of hierarchy. At the lowest level is a logic chip which has stored in an instruction memory a sequentially executed program of logical operators and operand addresses. The operand addresses refer to an input memory of the chip. The next highest level is the logic unit, on one circuit board, comprising a plurality of such logic chips. Each of the logic chips of the unit has its input memory receiving the same data from an input bus and a local bus and provides as its output one of the bits of an output bus and one of the bits of the local bus. At the next level, called a cluster, several logic units have their input and output buses interconnected by a plurality of switch units. All the logic chips of the several logic units operate in parallel with the exchange of data through the switch units. Several clusters can be combined into a super cluster by connecting together two or more sets of switch units.