Abstract: In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.

Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Abstract: A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Abstract: A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

Abstract: A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains a count of time slots over a period of time. The period of time corresponds to an amount of time between periodic power peaks of a memory operation. For each time slot, the storage module determines whether to commence a memory operation on one or more of the plurality of memory dies based on whether a power peak generated in the time slot by the memory operation would exceed a power threshold allowed for the time slot. Other embodiments are provided.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Abstract: Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

Abstract: Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.

Abstract: A data storage device includes a first memory die having memory cells and a first transfer data latch. The data storage device also includes a second memory die having second memory cells and a second transfer data latch. A bus is coupled to the first memory die and the second memory die. The data storage device also includes a controller coupled to the bus. The controller is configured to cause the first transfer data latch and the second transfer data latch to store first data responsive to sending the first data to the first memory die for programming of the first data to a first word line of the first memory cells.

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

Abstract: Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope. The counts may exclude one or more initial program voltages while the cells are programmed sufficiently to allow faster and slower cells to be distinguished, e.g., in a natural threshold voltage distribution. An erase depth can also be adjusted. The cells can be programmed in a separate evaluation or during programming of user data.

Abstract: A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.